1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/mmu.h> 25 26 struct fsl_e_tlb_entry tlb_table[] = { 27 /* TLB 0 - for temp stack in cache */ 28 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 29 MAS3_SX|MAS3_SW|MAS3_SR, 0, 30 0, 0, BOOKE_PAGESZ_4K, 0), 31 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 32 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 33 MAS3_SX|MAS3_SW|MAS3_SR, 0, 34 0, 0, BOOKE_PAGESZ_4K, 0), 35 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 36 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 37 MAS3_SX|MAS3_SW|MAS3_SR, 0, 38 0, 0, BOOKE_PAGESZ_4K, 0), 39 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 40 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 41 MAS3_SX|MAS3_SW|MAS3_SR, 0, 42 0, 0, BOOKE_PAGESZ_4K, 0), 43 44 /* TLB 1 */ 45 /* *I*** - Covers boot page */ 46 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 47 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 48 0, 0, BOOKE_PAGESZ_4K, 1), 49 50 /* *I*G* - CCSRBAR (PA) */ 51 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 52 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 53 0, 1, BOOKE_PAGESZ_1M, 1), 54 55 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 56 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 57 0, 3, BOOKE_PAGESZ_64M, 1), 58 59 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000, 60 CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000, 61 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 62 0, 4, BOOKE_PAGESZ_64M, 1), 63 64 #if defined(CONFIG_SYS_RAMBOOT) 65 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 66 MAS3_SX|MAS3_SW|MAS3_SR, 0, 67 0, 8, BOOKE_PAGESZ_1G, 1), 68 #endif 69 70 #ifdef CONFIG_PCI 71 /* *I*G* - PCI */ 72 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 73 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 74 0, 6, BOOKE_PAGESZ_256M, 1), 75 76 /* *I*G* - PCI I/O */ 77 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 78 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 79 0, 7, BOOKE_PAGESZ_64K, 1), 80 #endif 81 82 /* *I*G - Board FPGA */ 83 SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS, 84 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 85 0, 9, BOOKE_PAGESZ_256K, 1), 86 87 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 88 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 89 0, 5, BOOKE_PAGESZ_1M, 1), 90 }; 91 92 int num_tlb_entries = ARRAY_SIZE(tlb_table); 93