1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/mmu.h> 9 10 struct fsl_e_tlb_entry tlb_table[] = { 11 /* TLB 0 - for temp stack in cache */ 12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 13 MAS3_SX|MAS3_SW|MAS3_SR, 0, 14 0, 0, BOOKE_PAGESZ_4K, 0), 15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 16 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 17 MAS3_SX|MAS3_SW|MAS3_SR, 0, 18 0, 0, BOOKE_PAGESZ_4K, 0), 19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 20 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 21 MAS3_SX|MAS3_SW|MAS3_SR, 0, 22 0, 0, BOOKE_PAGESZ_4K, 0), 23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 24 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25 MAS3_SX|MAS3_SW|MAS3_SR, 0, 26 0, 0, BOOKE_PAGESZ_4K, 0), 27 28 /* TLB 1 */ 29 /* *I*** - Covers boot page */ 30 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 31 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 32 0, 0, BOOKE_PAGESZ_4K, 1), 33 #ifdef CONFIG_SPL_NAND_BOOT 34 SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, 35 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 36 0, 10, BOOKE_PAGESZ_4K, 1), 37 #endif 38 39 /* *I*G* - CCSRBAR (PA) */ 40 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 41 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 42 0, 1, BOOKE_PAGESZ_1M, 1), 43 44 /* CCSRBAR (DSP) */ 45 SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR, 46 CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, MAS3_SW|MAS3_SR, 47 MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1), 48 49 #ifndef CONFIG_SPL_BUILD 50 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 51 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 52 0, 3, BOOKE_PAGESZ_64M, 1), 53 54 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000, 55 CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000, 56 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 57 0, 4, BOOKE_PAGESZ_64M, 1), 58 59 #ifdef CONFIG_PCI 60 /* *I*G* - PCI */ 61 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 62 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 63 0, 6, BOOKE_PAGESZ_256M, 1), 64 65 /* *I*G* - PCI I/O */ 66 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 67 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 68 0, 7, BOOKE_PAGESZ_64K, 1), 69 #endif 70 #endif 71 72 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) 73 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 74 MAS3_SX|MAS3_SW|MAS3_SR, 0, 75 0, 8, BOOKE_PAGESZ_1G, 1), 76 #endif 77 78 #ifdef CONFIG_SYS_FPGA_BASE 79 /* *I*G - Board FPGA */ 80 SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS, 81 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 82 0, 9, BOOKE_PAGESZ_256K, 1), 83 #endif 84 85 #ifdef CONFIG_SYS_NAND_BASE_PHYS 86 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 87 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 88 0, 5, BOOKE_PAGESZ_1M, 1), 89 #endif 90 }; 91 92 int num_tlb_entries = ARRAY_SIZE(tlb_table); 93