1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <ns16550.h> 8 #include <asm/io.h> 9 #include <nand.h> 10 #include <linux/compiler.h> 11 #include <asm/fsl_law.h> 12 #include <fsl_ddr_sdram.h> 13 #include <asm/global_data.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 static void sdram_init(void) 18 { 19 struct ccsr_ddr __iomem *ddr = 20 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; 21 #if CONFIG_DDR_CLK_FREQ == 100000000 22 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); 23 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); 24 __raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg); 25 __raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2); 26 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); 27 28 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); 29 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); 30 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); 31 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); 32 __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); 33 __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); 34 __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); 35 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); 36 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); 37 38 __raw_writel(CONFIG_SYS_DDR_TIMING_4_800, &ddr->timing_cfg_4); 39 __raw_writel(CONFIG_SYS_DDR_TIMING_5_800, &ddr->timing_cfg_5); 40 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); 41 #elif CONFIG_DDR_CLK_FREQ == 133000000 42 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); 43 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); 44 __raw_writel(CONFIG_SYS_DDR_CONTROL_1333 | SDRAM_CFG_32_BE, &ddr->sdram_cfg); 45 __raw_writel(CONFIG_SYS_DDR_CONTROL_2_1333, &ddr->sdram_cfg_2); 46 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); 47 48 __raw_writel(CONFIG_SYS_DDR_TIMING_3_1333, &ddr->timing_cfg_3); 49 __raw_writel(CONFIG_SYS_DDR_TIMING_0_1333, &ddr->timing_cfg_0); 50 __raw_writel(CONFIG_SYS_DDR_TIMING_1_1333, &ddr->timing_cfg_1); 51 __raw_writel(CONFIG_SYS_DDR_TIMING_2_1333, &ddr->timing_cfg_2); 52 __raw_writel(CONFIG_SYS_DDR_MODE_1_1333, &ddr->sdram_mode); 53 __raw_writel(CONFIG_SYS_DDR_MODE_2_1333, &ddr->sdram_mode_2); 54 __raw_writel(CONFIG_SYS_DDR_INTERVAL_1333, &ddr->sdram_interval); 55 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_1333, &ddr->sdram_clk_cntl); 56 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_1333, &ddr->ddr_wrlvl_cntl); 57 58 __raw_writel(CONFIG_SYS_DDR_TIMING_4_1333, &ddr->timing_cfg_4); 59 __raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5); 60 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); 61 #else 62 puts("Not a valid DDR Freq Found! Please Reset\n"); 63 #endif 64 asm volatile("sync;isync"); 65 udelay(500); 66 67 /* Let the controller go */ 68 out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); 69 70 set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1); 71 } 72 73 void board_init_f(ulong bootflag) 74 { 75 u32 plat_ratio; 76 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 77 78 /* initialize selected port with appropriate baud rate */ 79 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; 80 plat_ratio >>= 1; 81 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; 82 83 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 84 gd->bus_clk / 16 / CONFIG_BAUDRATE); 85 86 puts("\nNAND boot... "); 87 88 /* Initialize the DDR3 */ 89 sdram_init(); 90 91 /* copy code to RAM and jump to it - this should not return */ 92 /* NOTE - code has to be copied out of NAND buffer before 93 * other blocks can be read. 94 */ 95 relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); 96 } 97 98 void board_init_r(gd_t *gd, ulong dest_addr) 99 { 100 nand_boot(); 101 } 102 103 void putc(char c) 104 { 105 if (c == '\n') 106 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); 107 108 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); 109 } 110 111 void puts(const char *str) 112 { 113 while (*str) 114 putc(*str++); 115 } 116