1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/mmu.h> 25 #include <asm/immap_85xx.h> 26 #include <asm/processor.h> 27 #include <asm/fsl_ddr_sdram.h> 28 #include <asm/fsl_ddr_dimm_params.h> 29 #include <asm/io.h> 30 #include <asm/fsl_law.h> 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 #ifndef CONFIG_SYS_DDR_RAW_TIMING 35 36 fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { 37 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, 38 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, 39 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, 40 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, 41 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, 42 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, 43 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, 44 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, 45 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, 46 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, 47 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, 48 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, 49 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, 50 .ddr_data_init = CONFIG_MEM_INIT_VALUE, 51 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, 52 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, 53 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, 54 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, 55 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, 56 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, 57 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800, 58 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, 59 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, 60 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 61 }; 62 63 fsl_ddr_cfg_regs_t ddr_cfg_regs_1333 = { 64 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, 65 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, 66 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, 67 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1333, 68 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1333, 69 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1333, 70 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1333, 71 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, 72 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, 73 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1333, 74 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1333, 75 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, 76 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1333, 77 .ddr_data_init = CONFIG_MEM_INIT_VALUE, 78 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1333, 79 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, 80 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, 81 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, 82 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, 83 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, 84 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_1333, 85 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, 86 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, 87 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 88 }; 89 90 91 fixed_ddr_parm_t fixed_ddr_parm_0[] = { 92 {750, 850, &ddr_cfg_regs_800}, 93 {1060, 1333, &ddr_cfg_regs_1333}, 94 {0, 0, NULL} 95 }; 96 97 /* 98 * Fixed sdram init -- doesn't use serial presence detect. 99 */ 100 phys_size_t fixed_sdram(void) 101 { 102 int i; 103 char buf[32]; 104 fsl_ddr_cfg_regs_t ddr_cfg_regs; 105 phys_size_t ddr_size; 106 ulong ddr_freq, ddr_freq_mhz; 107 108 ddr_freq = get_ddr_freq(0); 109 ddr_freq_mhz = ddr_freq / 1000000; 110 111 printf("Configuring DDR for %s MT/s data rate\n", 112 strmhz(buf, ddr_freq)); 113 114 for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { 115 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && 116 (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { 117 memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, 118 sizeof(ddr_cfg_regs)); 119 break; 120 } 121 } 122 123 if (fixed_ddr_parm_0[i].max_freq == 0) 124 panic("Unsupported DDR data rate %s MT/s data rate\n", 125 strmhz(buf, ddr_freq)); 126 127 ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 128 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); 129 130 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, 131 LAW_TRGT_IF_DDR_1) < 0) { 132 printf("ERROR setting Local Access Windows for DDR\n"); 133 return 0; 134 } 135 136 return ddr_size; 137 } 138 139 #else /* CONFIG_SYS_DDR_RAW_TIMING */ 140 /* Micron MT41J512M8_187E */ 141 dimm_params_t ddr_raw_timing = { 142 .n_ranks = 1, 143 .rank_density = 1073741824u, 144 .capacity = 1073741824u, 145 .primary_sdram_width = 32, 146 .ec_sdram_width = 0, 147 .registered_dimm = 0, 148 .mirrored_dimm = 0, 149 .n_row_addr = 15, 150 .n_col_addr = 10, 151 .n_banks_per_sdram_device = 8, 152 .edc_config = 0, 153 .burst_lengths_bitmask = 0x0c, 154 155 .tCKmin_X_ps = 1870, 156 .caslat_X = 0x1e << 4, /* 5,6,7,8 */ 157 .tAA_ps = 13125, 158 .tWR_ps = 15000, 159 .tRCD_ps = 13125, 160 .tRRD_ps = 7500, 161 .tRP_ps = 13125, 162 .tRAS_ps = 37500, 163 .tRC_ps = 50625, 164 .tRFC_ps = 160000, 165 .tWTR_ps = 7500, 166 .tRTP_ps = 7500, 167 .refresh_rate_ps = 7800000, 168 .tFAW_ps = 37500, 169 }; 170 171 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 172 unsigned int controller_number, 173 unsigned int dimm_number) 174 { 175 const char dimm_model[] = "Fixed DDR on board"; 176 177 if ((controller_number == 0) && (dimm_number == 0)) { 178 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 179 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 180 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 181 } 182 183 return 0; 184 } 185 186 void fsl_ddr_board_options(memctl_options_t *popts, 187 dimm_params_t *pdimm, 188 unsigned int ctrl_num) 189 { 190 int i; 191 popts->clk_adjust = 6; 192 popts->cpo_override = 0x1f; 193 popts->write_data_delay = 2; 194 popts->half_strength_driver_enable = 1; 195 /* Write leveling override */ 196 popts->wrlvl_en = 1; 197 popts->wrlvl_override = 1; 198 popts->wrlvl_sample = 0xf; 199 popts->wrlvl_start = 0x8; 200 popts->trwt_override = 1; 201 popts->trwt = 0; 202 203 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 204 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; 205 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; 206 } 207 } 208 209 #endif /* CONFIG_SYS_DDR_RAW_TIMING */ 210