1 /*
2  * Copyright 2013 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <asm/processor.h>
9 #include <asm/mmu.h>
10 #include <asm/cache.h>
11 #include <asm/immap_85xx.h>
12 #include <asm/io.h>
13 #include <miiphy.h>
14 #include <libfdt.h>
15 #include <fdt_support.h>
16 #include <fsl_mdio.h>
17 #include <tsec.h>
18 #include <mmc.h>
19 #include <netdev.h>
20 #include <fsl_ifc.h>
21 #include <hwconfig.h>
22 #include <i2c.h>
23 #include <fsl_ddr_sdram.h>
24 #include <jffs2/load_kernel.h>
25 #include <mtd_node.h>
26 #include <flash.h>
27 
28 #ifdef CONFIG_PCI
29 #include <pci.h>
30 #include <asm/fsl_pci.h>
31 #endif
32 
33 #include "../common/qixis.h"
34 DECLARE_GLOBAL_DATA_PTR;
35 
36 
37 int board_early_init_f(void)
38 {
39 	struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
40 
41 	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
42 
43 	return 0;
44 }
45 
46 void board_config_serdes_mux(void)
47 {
48 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
49 	u32 pordevsr = in_be32(&gur->pordevsr);
50 	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
51 				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
52 
53 	switch (srds_cfg) {
54 	/* PEX(1) PEX(2) CPRI 2 CPRI 1 */
55 	case  1:
56 	case  2:
57 	case  3:
58 	case  4:
59 	case  5:
60 	case 22:
61 	case 23:
62 	case 24:
63 	case 25:
64 	case 26:
65 		QIXIS_WRITE_I2C(brdcfg[4], 0x03);
66 		break;
67 
68 	/* PEX(1) PEX(2) SGMII1 CPRI 1 */
69 	case  6:
70 	case  7:
71 	case  8:
72 	case  9:
73 	case 10:
74 	case 27:
75 	case 28:
76 	case 29:
77 	case 30:
78 	case 31:
79 		QIXIS_WRITE_I2C(brdcfg[4], 0x01);
80 		break;
81 
82 	/* PEX(1) PEX(2) SGMII1 SGMII2 */
83 	case 11:
84 	case 32:
85 		QIXIS_WRITE_I2C(brdcfg[4], 0x00);
86 		break;
87 
88 	/* PEX(1) SGMII2 CPRI 2 CPRI 1 */
89 	case 12:
90 	case 13:
91 	case 14:
92 	case 15:
93 	case 16:
94 	case 33:
95 	case 34:
96 	case 35:
97 	case 36:
98 	case 37:
99 		QIXIS_WRITE_I2C(brdcfg[4], 0x07);
100 		break;
101 
102 	/* PEX(1) SGMII2 SGMII1 CPRI 1 */
103 	case 17:
104 	case 18:
105 	case 19:
106 	case 20:
107 	case 21:
108 	case 38:
109 	case 39:
110 	case 40:
111 	case 41:
112 	case 42:
113 		QIXIS_WRITE_I2C(brdcfg[4], 0x05);
114 		break;
115 
116 	/* SGMII1 SGMII2 CPRI 2 CPRI 1 */
117 	case 43:
118 	case 44:
119 	case 45:
120 	case 46:
121 	case 47:
122 		QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
123 		break;
124 
125 
126 	default:
127 		break;
128 	}
129 }
130 
131 /* Configure DSP DDR controller */
132 void dsp_ddr_configure(void)
133 {
134 	/*
135 	 *There are separate DDR-controllers for DSP and PowerPC side DDR.
136 	 *copy the ddr controller settings from PowerPC side DDR controller
137 	 *to the DSP DDR controller as connected DDR memories are similar.
138 	 */
139 	struct ccsr_ddr __iomem *pa_ddr =
140 			(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
141 	struct ccsr_ddr temp_ddr;
142 	struct ccsr_ddr __iomem *dsp_ddr =
143 			(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
144 
145 	memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
146 	temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
147 	temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
148 	memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
149 	dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
150 }
151 
152 int board_early_init_r(void)
153 {
154 #ifndef CONFIG_SYS_NO_FLASH
155 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
156 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
157 
158 	/*
159 	 * Remap Boot flash region to caching-inhibited
160 	 * so that flash can be erased properly.
161 	 */
162 
163 	/* Flush d-cache and invalidate i-cache of any FLASH data */
164 	flush_dcache();
165 	invalidate_icache();
166 
167 	if (flash_esel == -1) {
168 		/* very unlikely unless something is messed up */
169 		puts("Error: Could not find TLB for FLASH BASE\n");
170 		flash_esel = 2;	/* give our best effort to continue */
171 	} else {
172 		/* invalidate existing TLB entry for flash */
173 		disable_tlb(flash_esel);
174 	}
175 
176 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
177 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
178 			0, flash_esel, BOOKE_PAGESZ_64M, 1);
179 
180 	set_tlb(1, flashbase + 0x4000000,
181 			CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
182 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
183 			0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
184 #endif
185 	board_config_serdes_mux();
186 	dsp_ddr_configure();
187 	return 0;
188 }
189 
190 #ifdef CONFIG_PCI
191 void pci_init_board(void)
192 {
193 	fsl_pcie_init_board(0);
194 }
195 #endif /* ifdef CONFIG_PCI */
196 
197 int checkboard(void)
198 {
199 	struct cpu_type *cpu;
200 	u8 sw;
201 
202 	cpu = gd->arch.cpu;
203 	printf("Board: %sQDS\n", cpu->name);
204 
205 	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
206 	QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
207 
208 	sw = QIXIS_READ(brdcfg[0]);
209 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
210 
211 	printf("IFC chip select:");
212 	switch (sw) {
213 	case 0:
214 		printf("NOR\n");
215 		break;
216 	case 2:
217 		printf("Promjet\n");
218 		break;
219 	case 4:
220 		printf("NAND\n");
221 		break;
222 	default:
223 		printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
224 		break;
225 	}
226 
227 	return 0;
228 }
229 
230 int board_eth_init(bd_t *bis)
231 {
232 #ifdef CONFIG_TSEC_ENET
233 	struct fsl_pq_mdio_info mdio_info;
234 	struct tsec_info_struct tsec_info[4];
235 	int num = 0;
236 
237 #ifdef CONFIG_TSEC1
238 	SET_STD_TSEC_INFO(tsec_info[num], 1);
239 	num++;
240 
241 #endif
242 
243 #ifdef CONFIG_TSEC2
244 	SET_STD_TSEC_INFO(tsec_info[num], 2);
245 	num++;
246 #endif
247 
248 	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
249 	mdio_info.name = DEFAULT_MII_NAME;
250 
251 	fsl_pq_mdio_init(bis, &mdio_info);
252 	tsec_eth_init(bis, tsec_info, num);
253 #endif
254 
255 	#ifdef CONFIG_PCI
256 	pci_eth_init(bis);
257 	#endif
258 
259 	return 0;
260 }
261 
262 #define USBMUX_SEL_MASK		0xc0
263 #define USBMUX_SEL_UART2	0xc0
264 #define USBMUX_SEL_USB		0x40
265 #define SPIMUX_SEL_UART3	0x80
266 #define GPS_MUX_SEL_GPS		0x40
267 
268 #define TSEC_1588_CLKIN_MASK	0x03
269 #define CON_XCVR_REF_CLK	0x00
270 
271 int misc_init_r(void)
272 {
273 	u8 val;
274 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
275 	u32 porbmsr = in_be32(&gur->porbmsr);
276 	u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
277 
278 	/*Configure 1588 clock-in source from RF Card*/
279 	val = QIXIS_READ_I2C(brdcfg[5]);
280 	QIXIS_WRITE_I2C(brdcfg[5],
281 		(val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);
282 
283 	if (hwconfig("uart2") && hwconfig("usb1")) {
284 		printf("UART2 and USB cannot work together on the board\n");
285 		printf("Remove one from hwconfig and reset\n");
286 	} else {
287 		if (hwconfig("uart2")) {
288 			val = QIXIS_READ_I2C(brdcfg[5]);
289 			QIXIS_WRITE_I2C(brdcfg[5],
290 				(val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
291 			clrbits_be32(&gur->pmuxcr3,
292 						MPC85xx_PMUXCR3_USB_SEL_MASK);
293 			setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
294 		} else {
295 			/* By default USB should be selected.
296 			* Programming FPGA to select USB. */
297 			val = QIXIS_READ_I2C(brdcfg[5]);
298 			QIXIS_WRITE_I2C(brdcfg[5],
299 				(val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
300 		}
301 
302 	}
303 
304 	if (hwconfig("sim")) {
305 		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
306 			romloc == PORBMSR_ROMLOC_NOR ||
307 			romloc == PORBMSR_ROMLOC_SPI) {
308 
309 			val = QIXIS_READ_I2C(brdcfg[3]);
310 			QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
311 			clrbits_be32(&gur->pmuxcr,
312 				MPC85xx_PMUXCR0_SIM_SEL_MASK);
313 			setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
314 		}
315 	}
316 
317 	if (hwconfig("uart3")) {
318 		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
319 			romloc == PORBMSR_ROMLOC_NOR ||
320 			romloc == PORBMSR_ROMLOC_SDHC) {
321 
322 			/* UART3 and SPI1 (Flashes) are muxed together */
323 			val = QIXIS_READ_I2C(brdcfg[3]);
324 			QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
325 			clrbits_be32(&gur->pmuxcr3,
326 						MPC85xx_PMUXCR3_UART3_SEL_MASK);
327 			setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
328 
329 			/* MUX to select UART3 connection to J24 header
330 			 * or to GPS */
331 			val = QIXIS_READ_I2C(brdcfg[6]);
332 			if (hwconfig("gps"))
333 				QIXIS_WRITE_I2C(brdcfg[6],
334 						(val | GPS_MUX_SEL_GPS));
335 			else
336 				QIXIS_WRITE_I2C(brdcfg[6],
337 						(val & ~(GPS_MUX_SEL_GPS)));
338 		}
339 	}
340 	return 0;
341 }
342 
343 void fdt_del_node_compat(void *blob, const char *compatible)
344 {
345 	int err;
346 	int off = fdt_node_offset_by_compatible(blob, -1, compatible);
347 	if (off < 0) {
348 		printf("WARNING: could not find compatible node %s: %s.\n",
349 			compatible, fdt_strerror(off));
350 		return;
351 	}
352 	err = fdt_del_node(blob, off);
353 	if (err < 0) {
354 		printf("WARNING: could not remove %s: %s.\n",
355 			compatible, fdt_strerror(err));
356 	}
357 }
358 
359 #if defined(CONFIG_OF_BOARD_SETUP)
360 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
361 struct node_info nodes[] = {
362 	{ "cfi-flash",			MTD_DEV_TYPE_NOR,  },
363 	{ "fsl,ifc-nand",		MTD_DEV_TYPE_NAND, },
364 };
365 #endif
366 int ft_board_setup(void *blob, bd_t *bd)
367 {
368 	phys_addr_t base;
369 	phys_size_t size;
370 
371 	ft_cpu_setup(blob, bd);
372 
373 	base = getenv_bootm_low();
374 	size = getenv_bootm_size();
375 
376 	#if defined(CONFIG_PCI)
377 	FT_FSL_PCI_SETUP;
378 	#endif
379 
380 	fdt_fixup_memory(blob, (u64)base, (u64)size);
381 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
382 	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
383 #endif
384 
385 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
386 	u32 porbmsr = in_be32(&gur->porbmsr);
387 	u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
388 
389 	if (!(hwconfig("uart2") && hwconfig("usb1"))) {
390 		/* If uart2 is there in hwconfig remove usb node from
391 		 *  device tree */
392 
393 		if (hwconfig("uart2")) {
394 			/* remove dts usb node */
395 			fdt_del_node_compat(blob, "fsl-usb2-dr");
396 		} else {
397 			fsl_fdt_fixup_dr_usb(blob, bd);
398 			fdt_del_node_and_alias(blob, "serial2");
399 		}
400 	}
401 
402 	if (hwconfig("uart3")) {
403 		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
404 			romloc == PORBMSR_ROMLOC_NOR ||
405 			romloc == PORBMSR_ROMLOC_SDHC)
406 			/* Delete SPI node from the device tree */
407 				fdt_del_node_and_alias(blob, "spi1");
408 	} else
409 		fdt_del_node_and_alias(blob, "serial3");
410 
411 	if (hwconfig("sim")) {
412 		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
413 			romloc == PORBMSR_ROMLOC_NOR ||
414 			romloc == PORBMSR_ROMLOC_SPI) {
415 
416 			/* remove dts sdhc node */
417 			fdt_del_node_compat(blob, "fsl,esdhc");
418 		} else if (romloc == PORBMSR_ROMLOC_SDHC) {
419 
420 			/* remove dts sim node */
421 			fdt_del_node_compat(blob, "fsl,sim-v1.0");
422 			printf("SIM & SDHC can't work together on the board");
423 			printf("\nRemove sim from hwconfig and reset\n");
424 		}
425 	}
426 
427 	return 0;
428 }
429 #endif
430