1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/processor.h> 9 #include <asm/mmu.h> 10 #include <asm/cache.h> 11 #include <asm/immap_85xx.h> 12 #include <asm/io.h> 13 #include <miiphy.h> 14 #include <libfdt.h> 15 #include <fdt_support.h> 16 #include <fsl_mdio.h> 17 #include <tsec.h> 18 #include <mmc.h> 19 #include <netdev.h> 20 #include <fsl_ifc.h> 21 #include <hwconfig.h> 22 #include <i2c.h> 23 #include <fsl_ddr_sdram.h> 24 25 #ifdef CONFIG_PCI 26 #include <pci.h> 27 #include <asm/fsl_pci.h> 28 #endif 29 30 #include "../common/qixis.h" 31 DECLARE_GLOBAL_DATA_PTR; 32 33 34 int board_early_init_f(void) 35 { 36 struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR; 37 38 setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); 39 40 return 0; 41 } 42 43 void board_config_serdes_mux(void) 44 { 45 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 46 u32 pordevsr = in_be32(&gur->pordevsr); 47 u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 48 MPC85xx_PORDEVSR_IO_SEL_SHIFT; 49 50 switch (srds_cfg) { 51 /* PEX(1) PEX(2) CPRI 2 CPRI 1 */ 52 case 1: 53 case 2: 54 case 3: 55 case 4: 56 case 5: 57 case 22: 58 case 23: 59 case 24: 60 case 25: 61 case 26: 62 QIXIS_WRITE_I2C(brdcfg[4], 0x03); 63 break; 64 65 /* PEX(1) PEX(2) SGMII1 CPRI 1 */ 66 case 6: 67 case 7: 68 case 8: 69 case 9: 70 case 10: 71 case 27: 72 case 28: 73 case 29: 74 case 30: 75 case 31: 76 QIXIS_WRITE_I2C(brdcfg[4], 0x01); 77 break; 78 79 /* PEX(1) PEX(2) SGMII1 SGMII2 */ 80 case 11: 81 case 32: 82 QIXIS_WRITE_I2C(brdcfg[4], 0x00); 83 break; 84 85 /* PEX(1) SGMII2 CPRI 2 CPRI 1 */ 86 case 12: 87 case 13: 88 case 14: 89 case 15: 90 case 16: 91 case 33: 92 case 34: 93 case 35: 94 case 36: 95 case 37: 96 QIXIS_WRITE_I2C(brdcfg[4], 0x07); 97 break; 98 99 /* PEX(1) SGMII2 SGMII1 CPRI 1 */ 100 case 17: 101 case 18: 102 case 19: 103 case 20: 104 case 21: 105 case 38: 106 case 39: 107 case 40: 108 case 41: 109 case 42: 110 QIXIS_WRITE_I2C(brdcfg[4], 0x05); 111 break; 112 113 /* SGMII1 SGMII2 CPRI 2 CPRI 1 */ 114 case 43: 115 case 44: 116 case 45: 117 case 46: 118 case 47: 119 QIXIS_WRITE_I2C(brdcfg[4], 0x0F); 120 break; 121 122 123 default: 124 break; 125 } 126 } 127 128 /* Configure DSP DDR controller */ 129 void dsp_ddr_configure(void) 130 { 131 /* 132 *There are separate DDR-controllers for DSP and PowerPC side DDR. 133 *copy the ddr controller settings from PowerPC side DDR controller 134 *to the DSP DDR controller as connected DDR memories are similar. 135 */ 136 struct ccsr_ddr __iomem *pa_ddr = 137 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; 138 struct ccsr_ddr temp_ddr; 139 struct ccsr_ddr __iomem *dsp_ddr = 140 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR; 141 142 memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr)); 143 temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS; 144 temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN; 145 memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr)); 146 dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN; 147 } 148 149 int board_early_init_r(void) 150 { 151 #ifndef CONFIG_SYS_NO_FLASH 152 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 153 int flash_esel = find_tlb_idx((void *)flashbase, 1); 154 155 /* 156 * Remap Boot flash region to caching-inhibited 157 * so that flash can be erased properly. 158 */ 159 160 /* Flush d-cache and invalidate i-cache of any FLASH data */ 161 flush_dcache(); 162 invalidate_icache(); 163 164 if (flash_esel == -1) { 165 /* very unlikely unless something is messed up */ 166 puts("Error: Could not find TLB for FLASH BASE\n"); 167 flash_esel = 2; /* give our best effort to continue */ 168 } else { 169 /* invalidate existing TLB entry for flash */ 170 disable_tlb(flash_esel); 171 } 172 173 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 174 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 175 0, flash_esel, BOOKE_PAGESZ_64M, 1); 176 177 set_tlb(1, flashbase + 0x4000000, 178 CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000, 179 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 180 0, flash_esel+1, BOOKE_PAGESZ_64M, 1); 181 #endif 182 board_config_serdes_mux(); 183 dsp_ddr_configure(); 184 return 0; 185 } 186 187 #ifdef CONFIG_PCI 188 void pci_init_board(void) 189 { 190 fsl_pcie_init_board(0); 191 } 192 #endif /* ifdef CONFIG_PCI */ 193 194 int checkboard(void) 195 { 196 struct cpu_type *cpu; 197 u8 sw; 198 199 cpu = gd->arch.cpu; 200 printf("Board: %sQDS\n", cpu->name); 201 202 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n", 203 QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver)); 204 205 sw = QIXIS_READ(brdcfg[0]); 206 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 207 208 printf("IFC chip select:"); 209 switch (sw) { 210 case 0: 211 printf("NOR\n"); 212 break; 213 case 2: 214 printf("Promjet\n"); 215 break; 216 case 4: 217 printf("NAND\n"); 218 break; 219 default: 220 printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 221 break; 222 } 223 224 return 0; 225 } 226 227 #ifdef CONFIG_TSEC_ENET 228 int board_eth_init(bd_t *bis) 229 { 230 struct fsl_pq_mdio_info mdio_info; 231 struct tsec_info_struct tsec_info[4]; 232 int num = 0; 233 234 #ifdef CONFIG_TSEC1 235 SET_STD_TSEC_INFO(tsec_info[num], 1); 236 num++; 237 238 #endif 239 240 #ifdef CONFIG_TSEC2 241 SET_STD_TSEC_INFO(tsec_info[num], 2); 242 num++; 243 #endif 244 245 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 246 mdio_info.name = DEFAULT_MII_NAME; 247 248 fsl_pq_mdio_init(bis, &mdio_info); 249 tsec_eth_init(bis, tsec_info, num); 250 251 #ifdef CONFIG_PCI 252 pci_eth_init(bis); 253 #endif 254 255 return 0; 256 } 257 #endif 258 259 #define USBMUX_SEL_MASK 0xc0 260 #define USBMUX_SEL_UART2 0xc0 261 #define USBMUX_SEL_USB 0x40 262 #define SPIMUX_SEL_UART3 0x80 263 #define GPS_MUX_SEL_GPS 0x40 264 265 #define TSEC_1588_CLKIN_MASK 0x03 266 #define CON_XCVR_REF_CLK 0x00 267 268 int misc_init_r(void) 269 { 270 u8 val; 271 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 272 u32 porbmsr = in_be32(&gur->porbmsr); 273 u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; 274 275 /*Configure 1588 clock-in source from RF Card*/ 276 val = QIXIS_READ_I2C(brdcfg[5]); 277 QIXIS_WRITE_I2C(brdcfg[5], 278 (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK); 279 280 if (hwconfig("uart2") && hwconfig("usb1")) { 281 printf("UART2 and USB cannot work together on the board\n"); 282 printf("Remove one from hwconfig and reset\n"); 283 } else { 284 if (hwconfig("uart2")) { 285 val = QIXIS_READ_I2C(brdcfg[5]); 286 QIXIS_WRITE_I2C(brdcfg[5], 287 (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2); 288 clrbits_be32(&gur->pmuxcr3, 289 MPC85xx_PMUXCR3_USB_SEL_MASK); 290 setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL); 291 } else { 292 /* By default USB should be selected. 293 * Programming FPGA to select USB. */ 294 val = QIXIS_READ_I2C(brdcfg[5]); 295 QIXIS_WRITE_I2C(brdcfg[5], 296 (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB); 297 } 298 299 } 300 301 if (hwconfig("sim")) { 302 if (romloc == PORBMSR_ROMLOC_NAND_2K || 303 romloc == PORBMSR_ROMLOC_NOR || 304 romloc == PORBMSR_ROMLOC_SPI) { 305 306 val = QIXIS_READ_I2C(brdcfg[3]); 307 QIXIS_WRITE_I2C(brdcfg[3], val|0x10); 308 clrbits_be32(&gur->pmuxcr, 309 MPC85xx_PMUXCR0_SIM_SEL_MASK); 310 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL); 311 } 312 } 313 314 if (hwconfig("uart3")) { 315 if (romloc == PORBMSR_ROMLOC_NAND_2K || 316 romloc == PORBMSR_ROMLOC_NOR || 317 romloc == PORBMSR_ROMLOC_SDHC) { 318 319 /* UART3 and SPI1 (Flashes) are muxed together */ 320 val = QIXIS_READ_I2C(brdcfg[3]); 321 QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3)); 322 clrbits_be32(&gur->pmuxcr3, 323 MPC85xx_PMUXCR3_UART3_SEL_MASK); 324 setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL); 325 326 /* MUX to select UART3 connection to J24 header 327 * or to GPS */ 328 val = QIXIS_READ_I2C(brdcfg[6]); 329 if (hwconfig("gps")) 330 QIXIS_WRITE_I2C(brdcfg[6], 331 (val | GPS_MUX_SEL_GPS)); 332 else 333 QIXIS_WRITE_I2C(brdcfg[6], 334 (val & ~(GPS_MUX_SEL_GPS))); 335 } 336 } 337 return 0; 338 } 339 340 void fdt_del_node_compat(void *blob, const char *compatible) 341 { 342 int err; 343 int off = fdt_node_offset_by_compatible(blob, -1, compatible); 344 if (off < 0) { 345 printf("WARNING: could not find compatible node %s: %s.\n", 346 compatible, fdt_strerror(off)); 347 return; 348 } 349 err = fdt_del_node(blob, off); 350 if (err < 0) { 351 printf("WARNING: could not remove %s: %s.\n", 352 compatible, fdt_strerror(err)); 353 } 354 } 355 356 #if defined(CONFIG_OF_BOARD_SETUP) 357 void ft_board_setup(void *blob, bd_t *bd) 358 { 359 phys_addr_t base; 360 phys_size_t size; 361 362 ft_cpu_setup(blob, bd); 363 364 base = getenv_bootm_low(); 365 size = getenv_bootm_size(); 366 367 #if defined(CONFIG_PCI) 368 FT_FSL_PCI_SETUP; 369 #endif 370 371 fdt_fixup_memory(blob, (u64)base, (u64)size); 372 373 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 374 u32 porbmsr = in_be32(&gur->porbmsr); 375 u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; 376 377 if (!(hwconfig("uart2") && hwconfig("usb1"))) { 378 /* If uart2 is there in hwconfig remove usb node from 379 * device tree */ 380 381 if (hwconfig("uart2")) { 382 /* remove dts usb node */ 383 fdt_del_node_compat(blob, "fsl-usb2-dr"); 384 } else { 385 fdt_fixup_dr_usb(blob, bd); 386 fdt_del_node_and_alias(blob, "serial2"); 387 } 388 } 389 390 if (hwconfig("uart3")) { 391 if (romloc == PORBMSR_ROMLOC_NAND_2K || 392 romloc == PORBMSR_ROMLOC_NOR || 393 romloc == PORBMSR_ROMLOC_SDHC) 394 /* Delete SPI node from the device tree */ 395 fdt_del_node_and_alias(blob, "spi1"); 396 } else 397 fdt_del_node_and_alias(blob, "serial3"); 398 399 if (hwconfig("sim")) { 400 if (romloc == PORBMSR_ROMLOC_NAND_2K || 401 romloc == PORBMSR_ROMLOC_NOR || 402 romloc == PORBMSR_ROMLOC_SPI) { 403 404 /* remove dts sdhc node */ 405 fdt_del_node_compat(blob, "fsl,esdhc"); 406 } else if (romloc == PORBMSR_ROMLOC_SDHC) { 407 408 /* remove dts sim node */ 409 fdt_del_node_compat(blob, "fsl,sim-v1.0"); 410 printf("SIM & SDHC can't work together on the board"); 411 printf("\nRemove sim from hwconfig and reset\n"); 412 } 413 } 414 } 415 #endif 416