1 /*
2  * Copyright 2013 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <asm/processor.h>
9 #include <asm/mmu.h>
10 #include <asm/cache.h>
11 #include <asm/immap_85xx.h>
12 #include <asm/io.h>
13 #include <miiphy.h>
14 #include <libfdt.h>
15 #include <fdt_support.h>
16 #include <fsl_mdio.h>
17 #include <tsec.h>
18 #include <mmc.h>
19 #include <netdev.h>
20 #include <asm/fsl_ifc.h>
21 #include <hwconfig.h>
22 #include <i2c.h>
23 #include <asm/fsl_ddr_sdram.h>
24 
25 #ifdef CONFIG_PCI
26 #include <pci.h>
27 #include <asm/fsl_pci.h>
28 #endif
29 
30 #include "../common/qixis.h"
31 DECLARE_GLOBAL_DATA_PTR;
32 
33 
34 int board_early_init_f(void)
35 {
36 	struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
37 
38 	setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
39 
40 	return 0;
41 }
42 
43 void board_config_serdes_mux(void)
44 {
45 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
46 	u32 pordevsr = in_be32(&gur->pordevsr);
47 	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
48 				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
49 
50 	switch (srds_cfg) {
51 	/* PEX(1) PEX(2) CPRI 2 CPRI 1 */
52 	case  1:
53 	case  2:
54 	case  3:
55 	case  4:
56 	case  5:
57 	case 22:
58 	case 23:
59 	case 24:
60 	case 25:
61 	case 26:
62 		QIXIS_WRITE_I2C(brdcfg[4], 0x03);
63 		break;
64 
65 	/* PEX(1) PEX(2) SGMII1 CPRI 1 */
66 	case  6:
67 	case  7:
68 	case  8:
69 	case  9:
70 	case 10:
71 	case 27:
72 	case 28:
73 	case 29:
74 	case 30:
75 	case 31:
76 		QIXIS_WRITE_I2C(brdcfg[4], 0x01);
77 		break;
78 
79 	/* PEX(1) PEX(2) SGMII1 SGMII2 */
80 	case 11:
81 	case 32:
82 		QIXIS_WRITE_I2C(brdcfg[4], 0x00);
83 		break;
84 
85 	/* PEX(1) SGMII2 CPRI 2 CPRI 1 */
86 	case 12:
87 	case 13:
88 	case 14:
89 	case 15:
90 	case 16:
91 	case 33:
92 	case 34:
93 	case 35:
94 	case 36:
95 	case 37:
96 		QIXIS_WRITE_I2C(brdcfg[4], 0x07);
97 		break;
98 
99 	/* PEX(1) SGMII2 SGMII1 CPRI 1 */
100 	case 17:
101 	case 18:
102 	case 19:
103 	case 20:
104 	case 21:
105 	case 38:
106 	case 39:
107 	case 40:
108 	case 41:
109 	case 42:
110 		QIXIS_WRITE_I2C(brdcfg[4], 0x05);
111 		break;
112 
113 	/* SGMII1 SGMII2 CPRI 2 CPRI 1 */
114 	case 43:
115 	case 44:
116 	case 45:
117 	case 46:
118 	case 47:
119 		QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
120 		break;
121 
122 
123 	default:
124 		break;
125 	}
126 }
127 
128 /* Configure DSP DDR controller */
129 void dsp_ddr_configure(void)
130 {
131 	/*
132 	 *There are separate DDR-controllers for DSP and PowerPC side DDR.
133 	 *copy the ddr controller settings from PowerPC side DDR controller
134 	 *to the DSP DDR controller as connected DDR memories are similar.
135 	 */
136 	ccsr_ddr_t __iomem *pa_ddr =
137 			(ccsr_ddr_t __iomem *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
138 	ccsr_ddr_t temp_ddr;
139 	ccsr_ddr_t __iomem *dsp_ddr =
140 			(ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
141 
142 	memcpy(&temp_ddr, pa_ddr, sizeof(ccsr_ddr_t));
143 	temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
144 	temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
145 	memcpy(dsp_ddr, &temp_ddr, sizeof(ccsr_ddr_t));
146 	dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
147 }
148 
149 int board_early_init_r(void)
150 {
151 #ifndef CONFIG_SYS_NO_FLASH
152 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
153 	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
154 
155 	/*
156 	 * Remap Boot flash region to caching-inhibited
157 	 * so that flash can be erased properly.
158 	 */
159 
160 	/* Flush d-cache and invalidate i-cache of any FLASH data */
161 	flush_dcache();
162 	invalidate_icache();
163 
164 	/* invalidate existing TLB entry for flash */
165 	disable_tlb(flash_esel);
166 
167 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
168 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
169 			0, flash_esel, BOOKE_PAGESZ_64M, 1);
170 
171 	set_tlb(1, flashbase + 0x4000000,
172 			CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
173 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
174 			0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
175 #endif
176 	board_config_serdes_mux();
177 	dsp_ddr_configure();
178 	return 0;
179 }
180 
181 #ifdef CONFIG_PCI
182 void pci_init_board(void)
183 {
184 	fsl_pcie_init_board(0);
185 }
186 #endif /* ifdef CONFIG_PCI */
187 
188 int checkboard(void)
189 {
190 	struct cpu_type *cpu;
191 	u8 sw;
192 
193 	cpu = gd->arch.cpu;
194 	printf("Board: %sQDS\n", cpu->name);
195 
196 	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
197 	QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
198 
199 	sw = QIXIS_READ(brdcfg[0]);
200 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
201 
202 	printf("IFC chip select:");
203 	switch (sw) {
204 	case 0:
205 		printf("NOR\n");
206 		break;
207 	case 2:
208 		printf("Promjet\n");
209 		break;
210 	case 4:
211 		printf("NAND\n");
212 		break;
213 	default:
214 		printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
215 		break;
216 	}
217 
218 	return 0;
219 }
220 
221 #ifdef CONFIG_TSEC_ENET
222 int board_eth_init(bd_t *bis)
223 {
224 	struct fsl_pq_mdio_info mdio_info;
225 	struct tsec_info_struct tsec_info[4];
226 	int num = 0;
227 
228 #ifdef CONFIG_TSEC1
229 	SET_STD_TSEC_INFO(tsec_info[num], 1);
230 	num++;
231 
232 #endif
233 
234 #ifdef CONFIG_TSEC2
235 	SET_STD_TSEC_INFO(tsec_info[num], 2);
236 	num++;
237 #endif
238 
239 	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
240 	mdio_info.name = DEFAULT_MII_NAME;
241 
242 	fsl_pq_mdio_init(bis, &mdio_info);
243 	tsec_eth_init(bis, tsec_info, num);
244 
245 	#ifdef CONFIG_PCI
246 	pci_eth_init(bis);
247 	#endif
248 
249 	return 0;
250 }
251 #endif
252 
253 #define USBMUX_SEL_MASK		0xc0
254 #define USBMUX_SEL_UART2	0xc0
255 #define USBMUX_SEL_USB		0x40
256 #define SPIMUX_SEL_UART3	0x80
257 #define GPS_MUX_SEL_GPS		0x40
258 
259 #define TSEC_1588_CLKIN_MASK	0x03
260 #define CON_XCVR_REF_CLK	0x00
261 
262 int misc_init_r(void)
263 {
264 	u8 val;
265 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
266 	u32 porbmsr = in_be32(&gur->porbmsr);
267 	u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
268 
269 	/*Configure 1588 clock-in source from RF Card*/
270 	val = QIXIS_READ_I2C(brdcfg[5]);
271 	QIXIS_WRITE_I2C(brdcfg[5],
272 		(val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);
273 
274 	if (hwconfig("uart2") && hwconfig("usb1")) {
275 		printf("UART2 and USB cannot work together on the board\n");
276 		printf("Remove one from hwconfig and reset\n");
277 	} else {
278 		if (hwconfig("uart2")) {
279 			val = QIXIS_READ_I2C(brdcfg[5]);
280 			QIXIS_WRITE_I2C(brdcfg[5],
281 				(val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
282 			clrbits_be32(&gur->pmuxcr3,
283 						MPC85xx_PMUXCR3_USB_SEL_MASK);
284 			setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
285 		} else {
286 			/* By default USB should be selected.
287 			* Programming FPGA to select USB. */
288 			val = QIXIS_READ_I2C(brdcfg[5]);
289 			QIXIS_WRITE_I2C(brdcfg[5],
290 				(val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
291 		}
292 
293 	}
294 
295 	if (hwconfig("sim")) {
296 		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
297 			romloc == PORBMSR_ROMLOC_NOR ||
298 			romloc == PORBMSR_ROMLOC_SPI) {
299 
300 			val = QIXIS_READ_I2C(brdcfg[3]);
301 			QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
302 			clrbits_be32(&gur->pmuxcr,
303 				MPC85xx_PMUXCR0_SIM_SEL_MASK);
304 			setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
305 		}
306 	}
307 
308 	if (hwconfig("uart3")) {
309 		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
310 			romloc == PORBMSR_ROMLOC_NOR ||
311 			romloc == PORBMSR_ROMLOC_SDHC) {
312 
313 			/* UART3 and SPI1 (Flashes) are muxed together */
314 			val = QIXIS_READ_I2C(brdcfg[3]);
315 			QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
316 			clrbits_be32(&gur->pmuxcr3,
317 						MPC85xx_PMUXCR3_UART3_SEL_MASK);
318 			setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
319 
320 			/* MUX to select UART3 connection to J24 header
321 			 * or to GPS */
322 			val = QIXIS_READ_I2C(brdcfg[6]);
323 			if (hwconfig("gps"))
324 				QIXIS_WRITE_I2C(brdcfg[6],
325 						(val | GPS_MUX_SEL_GPS));
326 			else
327 				QIXIS_WRITE_I2C(brdcfg[6],
328 						(val & ~(GPS_MUX_SEL_GPS)));
329 		}
330 	}
331 	return 0;
332 }
333 
334 void fdt_del_node_compat(void *blob, const char *compatible)
335 {
336 	int err;
337 	int off = fdt_node_offset_by_compatible(blob, -1, compatible);
338 	if (off < 0) {
339 		printf("WARNING: could not find compatible node %s: %s.\n",
340 			compatible, fdt_strerror(off));
341 		return;
342 	}
343 	err = fdt_del_node(blob, off);
344 	if (err < 0) {
345 		printf("WARNING: could not remove %s: %s.\n",
346 			compatible, fdt_strerror(err));
347 	}
348 }
349 
350 #if defined(CONFIG_OF_BOARD_SETUP)
351 void ft_board_setup(void *blob, bd_t *bd)
352 {
353 	phys_addr_t base;
354 	phys_size_t size;
355 
356 	ft_cpu_setup(blob, bd);
357 
358 	base = getenv_bootm_low();
359 	size = getenv_bootm_size();
360 
361 	#if defined(CONFIG_PCI)
362 	FT_FSL_PCI_SETUP;
363 	#endif
364 
365 	fdt_fixup_memory(blob, (u64)base, (u64)size);
366 
367 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
368 	u32 porbmsr = in_be32(&gur->porbmsr);
369 	u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
370 
371 	if (!(hwconfig("uart2") && hwconfig("usb1"))) {
372 		/* If uart2 is there in hwconfig remove usb node from
373 		 *  device tree */
374 
375 		if (hwconfig("uart2")) {
376 			/* remove dts usb node */
377 			fdt_del_node_compat(blob, "fsl-usb2-dr");
378 		} else {
379 			fdt_fixup_dr_usb(blob, bd);
380 			fdt_del_node_and_alias(blob, "serial2");
381 		}
382 	}
383 
384 	if (hwconfig("uart3")) {
385 		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
386 			romloc == PORBMSR_ROMLOC_NOR ||
387 			romloc == PORBMSR_ROMLOC_SDHC)
388 			/* Delete SPI node from the device tree */
389 				fdt_del_node_and_alias(blob, "spi1");
390 	} else
391 		fdt_del_node_and_alias(blob, "serial3");
392 
393 	if (hwconfig("sim")) {
394 		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
395 			romloc == PORBMSR_ROMLOC_NOR ||
396 			romloc == PORBMSR_ROMLOC_SPI) {
397 
398 			/* remove dts sdhc node */
399 			fdt_del_node_compat(blob, "fsl,esdhc");
400 		} else if (romloc == PORBMSR_ROMLOC_SDHC) {
401 
402 			/* remove dts sim node */
403 			fdt_del_node_compat(blob, "fsl,sim-v1.0");
404 			printf("SIM & SDHC can't work together on the board");
405 			printf("\nRemove sim from hwconfig and reset\n");
406 		}
407 	}
408 }
409 #endif
410