1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/processor.h> 25 #include <asm/mmu.h> 26 #include <asm/cache.h> 27 #include <asm/immap_85xx.h> 28 #include <asm/io.h> 29 #include <miiphy.h> 30 #include <libfdt.h> 31 #include <fdt_support.h> 32 #include <fsl_mdio.h> 33 #include <tsec.h> 34 #include <mmc.h> 35 #include <netdev.h> 36 #include <asm/fsl_ifc.h> 37 #include <hwconfig.h> 38 #include <i2c.h> 39 #include <asm/fsl_ddr_sdram.h> 40 41 #ifdef CONFIG_PCI 42 #include <pci.h> 43 #include <asm/fsl_pci.h> 44 #endif 45 46 #include "../common/qixis.h" 47 DECLARE_GLOBAL_DATA_PTR; 48 49 50 int board_early_init_f(void) 51 { 52 struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR; 53 54 setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); 55 56 return 0; 57 } 58 59 void board_config_serdes_mux(void) 60 { 61 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 62 u32 pordevsr = in_be32(&gur->pordevsr); 63 u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 64 MPC85xx_PORDEVSR_IO_SEL_SHIFT; 65 66 switch (srds_cfg) { 67 /* PEX(1) PEX(2) CPRI 2 CPRI 1 */ 68 case 1: 69 case 2: 70 case 3: 71 case 4: 72 case 5: 73 case 22: 74 case 23: 75 case 24: 76 case 25: 77 case 26: 78 QIXIS_WRITE_I2C(brdcfg[4], 0x03); 79 break; 80 81 /* PEX(1) PEX(2) SGMII1 CPRI 1 */ 82 case 6: 83 case 7: 84 case 8: 85 case 9: 86 case 10: 87 case 27: 88 case 28: 89 case 29: 90 case 30: 91 case 31: 92 QIXIS_WRITE_I2C(brdcfg[4], 0x01); 93 break; 94 95 /* PEX(1) PEX(2) SGMII1 SGMII2 */ 96 case 11: 97 case 32: 98 QIXIS_WRITE_I2C(brdcfg[4], 0x00); 99 break; 100 101 /* PEX(1) SGMII2 CPRI 2 CPRI 1 */ 102 case 12: 103 case 13: 104 case 14: 105 case 15: 106 case 16: 107 case 33: 108 case 34: 109 case 35: 110 case 36: 111 case 37: 112 QIXIS_WRITE_I2C(brdcfg[4], 0x07); 113 break; 114 115 /* PEX(1) SGMII2 SGMII1 CPRI 1 */ 116 case 17: 117 case 18: 118 case 19: 119 case 20: 120 case 21: 121 case 38: 122 case 39: 123 case 40: 124 case 41: 125 case 42: 126 QIXIS_WRITE_I2C(brdcfg[4], 0x05); 127 break; 128 129 /* SGMII1 SGMII2 CPRI 2 CPRI 1 */ 130 case 43: 131 case 44: 132 case 45: 133 case 46: 134 case 47: 135 QIXIS_WRITE_I2C(brdcfg[4], 0x0F); 136 break; 137 138 139 default: 140 break; 141 } 142 } 143 144 int board_early_init_r(void) 145 { 146 #ifndef CONFIG_SYS_NO_FLASH 147 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 148 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 149 150 /* 151 * Remap Boot flash region to caching-inhibited 152 * so that flash can be erased properly. 153 */ 154 155 /* Flush d-cache and invalidate i-cache of any FLASH data */ 156 flush_dcache(); 157 invalidate_icache(); 158 159 /* invalidate existing TLB entry for flash */ 160 disable_tlb(flash_esel); 161 162 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 163 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 164 0, flash_esel, BOOKE_PAGESZ_64M, 1); 165 166 set_tlb(1, flashbase + 0x4000000, 167 CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000, 168 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 169 0, flash_esel+1, BOOKE_PAGESZ_64M, 1); 170 #endif 171 board_config_serdes_mux(); 172 return 0; 173 } 174 175 #ifdef CONFIG_PCI 176 void pci_init_board(void) 177 { 178 fsl_pcie_init_board(0); 179 } 180 #endif /* ifdef CONFIG_PCI */ 181 182 int checkboard(void) 183 { 184 struct cpu_type *cpu; 185 u8 sw; 186 187 cpu = gd->arch.cpu; 188 printf("Board: %sQDS\n", cpu->name); 189 190 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n", 191 QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver)); 192 193 sw = QIXIS_READ(brdcfg[0]); 194 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 195 196 printf("IFC chip select:"); 197 switch (sw) { 198 case 0: 199 printf("NOR\n"); 200 break; 201 case 2: 202 printf("Promjet\n"); 203 break; 204 case 4: 205 printf("NAND\n"); 206 break; 207 default: 208 printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 209 break; 210 } 211 212 return 0; 213 } 214 215 #ifdef CONFIG_TSEC_ENET 216 int board_eth_init(bd_t *bis) 217 { 218 struct fsl_pq_mdio_info mdio_info; 219 struct tsec_info_struct tsec_info[4]; 220 int num = 0; 221 222 #ifdef CONFIG_TSEC1 223 SET_STD_TSEC_INFO(tsec_info[num], 1); 224 num++; 225 226 #endif 227 228 #ifdef CONFIG_TSEC2 229 SET_STD_TSEC_INFO(tsec_info[num], 2); 230 num++; 231 #endif 232 233 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 234 mdio_info.name = DEFAULT_MII_NAME; 235 236 fsl_pq_mdio_init(bis, &mdio_info); 237 tsec_eth_init(bis, tsec_info, num); 238 239 #ifdef CONFIG_PCI 240 pci_eth_init(bis); 241 #endif 242 243 return 0; 244 } 245 #endif 246 247 #define USBMUX_SEL_MASK 0xc0 248 #define USBMUX_SEL_UART2 0xc0 249 #define USBMUX_SEL_USB 0x40 250 #define SPIMUX_SEL_UART3 0x80 251 #define GPS_MUX_SEL_GPS 0x40 252 253 #define TSEC_1588_CLKIN_MASK 0x03 254 #define CON_XCVR_REF_CLK 0x00 255 256 int misc_init_r(void) 257 { 258 u8 val; 259 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 260 u32 porbmsr = in_be32(&gur->porbmsr); 261 u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; 262 263 /*Configure 1588 clock-in source from RF Card*/ 264 val = QIXIS_READ_I2C(brdcfg[5]); 265 QIXIS_WRITE_I2C(brdcfg[5], 266 (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK); 267 268 if (hwconfig("uart2") && hwconfig("usb1")) { 269 printf("UART2 and USB cannot work together on the board\n"); 270 printf("Remove one from hwconfig and reset\n"); 271 } else { 272 if (hwconfig("uart2")) { 273 val = QIXIS_READ_I2C(brdcfg[5]); 274 QIXIS_WRITE_I2C(brdcfg[5], 275 (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2); 276 clrbits_be32(&gur->pmuxcr3, 277 MPC85xx_PMUXCR3_USB_SEL_MASK); 278 setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL); 279 } else { 280 /* By default USB should be selected. 281 * Programming FPGA to select USB. */ 282 val = QIXIS_READ_I2C(brdcfg[5]); 283 QIXIS_WRITE_I2C(brdcfg[5], 284 (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB); 285 } 286 287 } 288 289 if (hwconfig("sim")) { 290 if (romloc == PORBMSR_ROMLOC_NAND_2K || 291 romloc == PORBMSR_ROMLOC_NOR || 292 romloc == PORBMSR_ROMLOC_SPI) { 293 294 val = QIXIS_READ_I2C(brdcfg[3]); 295 QIXIS_WRITE_I2C(brdcfg[3], val|0x10); 296 clrbits_be32(&gur->pmuxcr, 297 MPC85xx_PMUXCR0_SIM_SEL_MASK); 298 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL); 299 } 300 } 301 302 if (hwconfig("uart3")) { 303 if (romloc == PORBMSR_ROMLOC_NAND_2K || 304 romloc == PORBMSR_ROMLOC_NOR || 305 romloc == PORBMSR_ROMLOC_SDHC) { 306 307 /* UART3 and SPI1 (Flashes) are muxed together */ 308 val = QIXIS_READ_I2C(brdcfg[3]); 309 QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3)); 310 clrbits_be32(&gur->pmuxcr3, 311 MPC85xx_PMUXCR3_UART3_SEL_MASK); 312 setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL); 313 314 /* MUX to select UART3 connection to J24 header 315 * or to GPS */ 316 val = QIXIS_READ_I2C(brdcfg[6]); 317 if (hwconfig("gps")) 318 QIXIS_WRITE_I2C(brdcfg[6], 319 (val | GPS_MUX_SEL_GPS)); 320 else 321 QIXIS_WRITE_I2C(brdcfg[6], 322 (val & ~(GPS_MUX_SEL_GPS))); 323 } 324 } 325 return 0; 326 } 327 328 void fdt_del_node_compat(void *blob, const char *compatible) 329 { 330 int err; 331 int off = fdt_node_offset_by_compatible(blob, -1, compatible); 332 if (off < 0) { 333 printf("WARNING: could not find compatible node %s: %s.\n", 334 compatible, fdt_strerror(off)); 335 return; 336 } 337 err = fdt_del_node(blob, off); 338 if (err < 0) { 339 printf("WARNING: could not remove %s: %s.\n", 340 compatible, fdt_strerror(err)); 341 } 342 } 343 344 #if defined(CONFIG_OF_BOARD_SETUP) 345 void ft_board_setup(void *blob, bd_t *bd) 346 { 347 phys_addr_t base; 348 phys_size_t size; 349 350 ft_cpu_setup(blob, bd); 351 352 base = getenv_bootm_low(); 353 size = getenv_bootm_size(); 354 355 #if defined(CONFIG_PCI) 356 FT_FSL_PCI_SETUP; 357 #endif 358 359 fdt_fixup_memory(blob, (u64)base, (u64)size); 360 361 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 362 u32 porbmsr = in_be32(&gur->porbmsr); 363 u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; 364 365 if (!(hwconfig("uart2") && hwconfig("usb1"))) { 366 /* If uart2 is there in hwconfig remove usb node from 367 * device tree */ 368 369 if (hwconfig("uart2")) { 370 /* remove dts usb node */ 371 fdt_del_node_compat(blob, "fsl-usb2-dr"); 372 } else { 373 fdt_fixup_dr_usb(blob, bd); 374 fdt_del_node_and_alias(blob, "serial2"); 375 } 376 } 377 378 if (hwconfig("uart3")) { 379 if (romloc == PORBMSR_ROMLOC_NAND_2K || 380 romloc == PORBMSR_ROMLOC_NOR || 381 romloc == PORBMSR_ROMLOC_SDHC) 382 /* Delete SPI node from the device tree */ 383 fdt_del_node_and_alias(blob, "spi1"); 384 } else 385 fdt_del_node_and_alias(blob, "serial3"); 386 387 if (hwconfig("sim")) { 388 if (romloc == PORBMSR_ROMLOC_NAND_2K || 389 romloc == PORBMSR_ROMLOC_NOR || 390 romloc == PORBMSR_ROMLOC_SPI) { 391 392 /* remove dts sdhc node */ 393 fdt_del_node_compat(blob, "fsl,esdhc"); 394 } else if (romloc == PORBMSR_ROMLOC_SDHC) { 395 396 /* remove dts sim node */ 397 fdt_del_node_compat(blob, "fsl,sim-v1.0"); 398 printf("SIM & SDHC can't work together on the board"); 399 printf("\nRemove sim from hwconfig and reset\n"); 400 } 401 } 402 } 403 #endif 404