141d91011SPrabhakar Kushwaha /* 241d91011SPrabhakar Kushwaha * Copyright 2013 Freescale Semiconductor, Inc. 341d91011SPrabhakar Kushwaha * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 541d91011SPrabhakar Kushwaha */ 641d91011SPrabhakar Kushwaha 741d91011SPrabhakar Kushwaha #include <common.h> 841d91011SPrabhakar Kushwaha #include <asm/processor.h> 941d91011SPrabhakar Kushwaha #include <asm/mmu.h> 1041d91011SPrabhakar Kushwaha #include <asm/cache.h> 1141d91011SPrabhakar Kushwaha #include <asm/immap_85xx.h> 1241d91011SPrabhakar Kushwaha #include <asm/io.h> 1341d91011SPrabhakar Kushwaha #include <miiphy.h> 1441d91011SPrabhakar Kushwaha #include <libfdt.h> 1541d91011SPrabhakar Kushwaha #include <fdt_support.h> 1641d91011SPrabhakar Kushwaha #include <fsl_mdio.h> 1741d91011SPrabhakar Kushwaha #include <tsec.h> 1841d91011SPrabhakar Kushwaha #include <mmc.h> 1941d91011SPrabhakar Kushwaha #include <netdev.h> 200b66513bSYork Sun #include <fsl_ifc.h> 2141d91011SPrabhakar Kushwaha #include <hwconfig.h> 2241d91011SPrabhakar Kushwaha #include <i2c.h> 235614e71bSYork Sun #include <fsl_ddr_sdram.h> 2442a9e2feSAshish Kumar #include <jffs2/load_kernel.h> 2542a9e2feSAshish Kumar #include <mtd_node.h> 2642a9e2feSAshish Kumar #include <flash.h> 2741d91011SPrabhakar Kushwaha 2841d91011SPrabhakar Kushwaha #ifdef CONFIG_PCI 2941d91011SPrabhakar Kushwaha #include <pci.h> 3041d91011SPrabhakar Kushwaha #include <asm/fsl_pci.h> 3141d91011SPrabhakar Kushwaha #endif 3241d91011SPrabhakar Kushwaha 3341d91011SPrabhakar Kushwaha #include "../common/qixis.h" 3441d91011SPrabhakar Kushwaha DECLARE_GLOBAL_DATA_PTR; 3541d91011SPrabhakar Kushwaha 3641d91011SPrabhakar Kushwaha 3741d91011SPrabhakar Kushwaha int board_early_init_f(void) 3841d91011SPrabhakar Kushwaha { 3939b0bbbbSJaiprakash Singh struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; 4041d91011SPrabhakar Kushwaha 4139b0bbbbSJaiprakash Singh setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); 4241d91011SPrabhakar Kushwaha 4341d91011SPrabhakar Kushwaha return 0; 4441d91011SPrabhakar Kushwaha } 4541d91011SPrabhakar Kushwaha 4641d91011SPrabhakar Kushwaha void board_config_serdes_mux(void) 4741d91011SPrabhakar Kushwaha { 4841d91011SPrabhakar Kushwaha ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 4941d91011SPrabhakar Kushwaha u32 pordevsr = in_be32(&gur->pordevsr); 5041d91011SPrabhakar Kushwaha u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 5141d91011SPrabhakar Kushwaha MPC85xx_PORDEVSR_IO_SEL_SHIFT; 5241d91011SPrabhakar Kushwaha 5341d91011SPrabhakar Kushwaha switch (srds_cfg) { 5441d91011SPrabhakar Kushwaha /* PEX(1) PEX(2) CPRI 2 CPRI 1 */ 5541d91011SPrabhakar Kushwaha case 1: 5641d91011SPrabhakar Kushwaha case 2: 5741d91011SPrabhakar Kushwaha case 3: 5841d91011SPrabhakar Kushwaha case 4: 5941d91011SPrabhakar Kushwaha case 5: 6041d91011SPrabhakar Kushwaha case 22: 6141d91011SPrabhakar Kushwaha case 23: 6241d91011SPrabhakar Kushwaha case 24: 6341d91011SPrabhakar Kushwaha case 25: 6441d91011SPrabhakar Kushwaha case 26: 6541d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[4], 0x03); 6641d91011SPrabhakar Kushwaha break; 6741d91011SPrabhakar Kushwaha 6841d91011SPrabhakar Kushwaha /* PEX(1) PEX(2) SGMII1 CPRI 1 */ 6941d91011SPrabhakar Kushwaha case 6: 7041d91011SPrabhakar Kushwaha case 7: 7141d91011SPrabhakar Kushwaha case 8: 7241d91011SPrabhakar Kushwaha case 9: 7341d91011SPrabhakar Kushwaha case 10: 7441d91011SPrabhakar Kushwaha case 27: 7541d91011SPrabhakar Kushwaha case 28: 7641d91011SPrabhakar Kushwaha case 29: 7741d91011SPrabhakar Kushwaha case 30: 7841d91011SPrabhakar Kushwaha case 31: 7941d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[4], 0x01); 8041d91011SPrabhakar Kushwaha break; 8141d91011SPrabhakar Kushwaha 8241d91011SPrabhakar Kushwaha /* PEX(1) PEX(2) SGMII1 SGMII2 */ 8341d91011SPrabhakar Kushwaha case 11: 8441d91011SPrabhakar Kushwaha case 32: 8541d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[4], 0x00); 8641d91011SPrabhakar Kushwaha break; 8741d91011SPrabhakar Kushwaha 8841d91011SPrabhakar Kushwaha /* PEX(1) SGMII2 CPRI 2 CPRI 1 */ 8941d91011SPrabhakar Kushwaha case 12: 9041d91011SPrabhakar Kushwaha case 13: 9141d91011SPrabhakar Kushwaha case 14: 9241d91011SPrabhakar Kushwaha case 15: 9341d91011SPrabhakar Kushwaha case 16: 9441d91011SPrabhakar Kushwaha case 33: 9541d91011SPrabhakar Kushwaha case 34: 9641d91011SPrabhakar Kushwaha case 35: 9741d91011SPrabhakar Kushwaha case 36: 9841d91011SPrabhakar Kushwaha case 37: 9941d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[4], 0x07); 10041d91011SPrabhakar Kushwaha break; 10141d91011SPrabhakar Kushwaha 10241d91011SPrabhakar Kushwaha /* PEX(1) SGMII2 SGMII1 CPRI 1 */ 10341d91011SPrabhakar Kushwaha case 17: 10441d91011SPrabhakar Kushwaha case 18: 10541d91011SPrabhakar Kushwaha case 19: 10641d91011SPrabhakar Kushwaha case 20: 10741d91011SPrabhakar Kushwaha case 21: 10841d91011SPrabhakar Kushwaha case 38: 10941d91011SPrabhakar Kushwaha case 39: 11041d91011SPrabhakar Kushwaha case 40: 11141d91011SPrabhakar Kushwaha case 41: 11241d91011SPrabhakar Kushwaha case 42: 11341d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[4], 0x05); 11441d91011SPrabhakar Kushwaha break; 11541d91011SPrabhakar Kushwaha 11641d91011SPrabhakar Kushwaha /* SGMII1 SGMII2 CPRI 2 CPRI 1 */ 11741d91011SPrabhakar Kushwaha case 43: 11841d91011SPrabhakar Kushwaha case 44: 11941d91011SPrabhakar Kushwaha case 45: 12041d91011SPrabhakar Kushwaha case 46: 12141d91011SPrabhakar Kushwaha case 47: 12241d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[4], 0x0F); 12341d91011SPrabhakar Kushwaha break; 12441d91011SPrabhakar Kushwaha 12541d91011SPrabhakar Kushwaha 12641d91011SPrabhakar Kushwaha default: 12741d91011SPrabhakar Kushwaha break; 12841d91011SPrabhakar Kushwaha } 12941d91011SPrabhakar Kushwaha } 13041d91011SPrabhakar Kushwaha 131f9d379a7SPriyanka Jain /* Configure DSP DDR controller */ 132f9d379a7SPriyanka Jain void dsp_ddr_configure(void) 133f9d379a7SPriyanka Jain { 134f9d379a7SPriyanka Jain /* 135f9d379a7SPriyanka Jain *There are separate DDR-controllers for DSP and PowerPC side DDR. 136f9d379a7SPriyanka Jain *copy the ddr controller settings from PowerPC side DDR controller 137f9d379a7SPriyanka Jain *to the DSP DDR controller as connected DDR memories are similar. 138f9d379a7SPriyanka Jain */ 1399a17eb5bSYork Sun struct ccsr_ddr __iomem *pa_ddr = 1409a17eb5bSYork Sun (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; 1419a17eb5bSYork Sun struct ccsr_ddr temp_ddr; 1429a17eb5bSYork Sun struct ccsr_ddr __iomem *dsp_ddr = 1439a17eb5bSYork Sun (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR; 144f9d379a7SPriyanka Jain 1459a17eb5bSYork Sun memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr)); 146f9d379a7SPriyanka Jain temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS; 147f9d379a7SPriyanka Jain temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN; 1489a17eb5bSYork Sun memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr)); 149f9d379a7SPriyanka Jain dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN; 150f9d379a7SPriyanka Jain } 151f9d379a7SPriyanka Jain 15241d91011SPrabhakar Kushwaha int board_early_init_r(void) 15341d91011SPrabhakar Kushwaha { 154*e856bdcfSMasahiro Yamada #ifdef CONFIG_MTD_NOR_FLASH 15541d91011SPrabhakar Kushwaha const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 1569d045682SYork Sun int flash_esel = find_tlb_idx((void *)flashbase, 1); 15741d91011SPrabhakar Kushwaha 15841d91011SPrabhakar Kushwaha /* 15941d91011SPrabhakar Kushwaha * Remap Boot flash region to caching-inhibited 16041d91011SPrabhakar Kushwaha * so that flash can be erased properly. 16141d91011SPrabhakar Kushwaha */ 16241d91011SPrabhakar Kushwaha 16341d91011SPrabhakar Kushwaha /* Flush d-cache and invalidate i-cache of any FLASH data */ 16441d91011SPrabhakar Kushwaha flush_dcache(); 16541d91011SPrabhakar Kushwaha invalidate_icache(); 16641d91011SPrabhakar Kushwaha 1679d045682SYork Sun if (flash_esel == -1) { 1689d045682SYork Sun /* very unlikely unless something is messed up */ 1699d045682SYork Sun puts("Error: Could not find TLB for FLASH BASE\n"); 1709d045682SYork Sun flash_esel = 2; /* give our best effort to continue */ 1719d045682SYork Sun } else { 17241d91011SPrabhakar Kushwaha /* invalidate existing TLB entry for flash */ 17341d91011SPrabhakar Kushwaha disable_tlb(flash_esel); 1749d045682SYork Sun } 17541d91011SPrabhakar Kushwaha 17641d91011SPrabhakar Kushwaha set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 17741d91011SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 17841d91011SPrabhakar Kushwaha 0, flash_esel, BOOKE_PAGESZ_64M, 1); 17941d91011SPrabhakar Kushwaha 18041d91011SPrabhakar Kushwaha set_tlb(1, flashbase + 0x4000000, 18141d91011SPrabhakar Kushwaha CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000, 18241d91011SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 18341d91011SPrabhakar Kushwaha 0, flash_esel+1, BOOKE_PAGESZ_64M, 1); 18441d91011SPrabhakar Kushwaha #endif 18541d91011SPrabhakar Kushwaha board_config_serdes_mux(); 186f9d379a7SPriyanka Jain dsp_ddr_configure(); 18741d91011SPrabhakar Kushwaha return 0; 18841d91011SPrabhakar Kushwaha } 18941d91011SPrabhakar Kushwaha 19041d91011SPrabhakar Kushwaha #ifdef CONFIG_PCI 19141d91011SPrabhakar Kushwaha void pci_init_board(void) 19241d91011SPrabhakar Kushwaha { 19341d91011SPrabhakar Kushwaha fsl_pcie_init_board(0); 19441d91011SPrabhakar Kushwaha } 19541d91011SPrabhakar Kushwaha #endif /* ifdef CONFIG_PCI */ 19641d91011SPrabhakar Kushwaha 19741d91011SPrabhakar Kushwaha int checkboard(void) 19841d91011SPrabhakar Kushwaha { 19941d91011SPrabhakar Kushwaha struct cpu_type *cpu; 20041d91011SPrabhakar Kushwaha u8 sw; 20141d91011SPrabhakar Kushwaha 20267ac13b1SSimon Glass cpu = gd->arch.cpu; 20341d91011SPrabhakar Kushwaha printf("Board: %sQDS\n", cpu->name); 20441d91011SPrabhakar Kushwaha 20541d91011SPrabhakar Kushwaha printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n", 20641d91011SPrabhakar Kushwaha QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver)); 20741d91011SPrabhakar Kushwaha 20841d91011SPrabhakar Kushwaha sw = QIXIS_READ(brdcfg[0]); 20941d91011SPrabhakar Kushwaha sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 21041d91011SPrabhakar Kushwaha 21141d91011SPrabhakar Kushwaha printf("IFC chip select:"); 21241d91011SPrabhakar Kushwaha switch (sw) { 21341d91011SPrabhakar Kushwaha case 0: 21441d91011SPrabhakar Kushwaha printf("NOR\n"); 21541d91011SPrabhakar Kushwaha break; 21641d91011SPrabhakar Kushwaha case 2: 21741d91011SPrabhakar Kushwaha printf("Promjet\n"); 21841d91011SPrabhakar Kushwaha break; 21941d91011SPrabhakar Kushwaha case 4: 22041d91011SPrabhakar Kushwaha printf("NAND\n"); 22141d91011SPrabhakar Kushwaha break; 22241d91011SPrabhakar Kushwaha default: 22341d91011SPrabhakar Kushwaha printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 22441d91011SPrabhakar Kushwaha break; 22541d91011SPrabhakar Kushwaha } 22641d91011SPrabhakar Kushwaha 22741d91011SPrabhakar Kushwaha return 0; 22841d91011SPrabhakar Kushwaha } 22941d91011SPrabhakar Kushwaha 23041d91011SPrabhakar Kushwaha int board_eth_init(bd_t *bis) 23141d91011SPrabhakar Kushwaha { 23289c97842SBin Meng #ifdef CONFIG_TSEC_ENET 23341d91011SPrabhakar Kushwaha struct fsl_pq_mdio_info mdio_info; 23441d91011SPrabhakar Kushwaha struct tsec_info_struct tsec_info[4]; 23541d91011SPrabhakar Kushwaha int num = 0; 23641d91011SPrabhakar Kushwaha 23741d91011SPrabhakar Kushwaha #ifdef CONFIG_TSEC1 23841d91011SPrabhakar Kushwaha SET_STD_TSEC_INFO(tsec_info[num], 1); 23941d91011SPrabhakar Kushwaha num++; 24041d91011SPrabhakar Kushwaha 24141d91011SPrabhakar Kushwaha #endif 24241d91011SPrabhakar Kushwaha 24341d91011SPrabhakar Kushwaha #ifdef CONFIG_TSEC2 24441d91011SPrabhakar Kushwaha SET_STD_TSEC_INFO(tsec_info[num], 2); 24541d91011SPrabhakar Kushwaha num++; 24641d91011SPrabhakar Kushwaha #endif 24741d91011SPrabhakar Kushwaha 24841d91011SPrabhakar Kushwaha mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 24941d91011SPrabhakar Kushwaha mdio_info.name = DEFAULT_MII_NAME; 25041d91011SPrabhakar Kushwaha 25141d91011SPrabhakar Kushwaha fsl_pq_mdio_init(bis, &mdio_info); 25241d91011SPrabhakar Kushwaha tsec_eth_init(bis, tsec_info, num); 25389c97842SBin Meng #endif 25441d91011SPrabhakar Kushwaha 25541d91011SPrabhakar Kushwaha #ifdef CONFIG_PCI 25641d91011SPrabhakar Kushwaha pci_eth_init(bis); 25741d91011SPrabhakar Kushwaha #endif 25841d91011SPrabhakar Kushwaha 25941d91011SPrabhakar Kushwaha return 0; 26041d91011SPrabhakar Kushwaha } 26141d91011SPrabhakar Kushwaha 26241d91011SPrabhakar Kushwaha #define USBMUX_SEL_MASK 0xc0 26341d91011SPrabhakar Kushwaha #define USBMUX_SEL_UART2 0xc0 26441d91011SPrabhakar Kushwaha #define USBMUX_SEL_USB 0x40 26541d91011SPrabhakar Kushwaha #define SPIMUX_SEL_UART3 0x80 26641d91011SPrabhakar Kushwaha #define GPS_MUX_SEL_GPS 0x40 26741d91011SPrabhakar Kushwaha 26841d91011SPrabhakar Kushwaha #define TSEC_1588_CLKIN_MASK 0x03 26941d91011SPrabhakar Kushwaha #define CON_XCVR_REF_CLK 0x00 27041d91011SPrabhakar Kushwaha 27141d91011SPrabhakar Kushwaha int misc_init_r(void) 27241d91011SPrabhakar Kushwaha { 27341d91011SPrabhakar Kushwaha u8 val; 27441d91011SPrabhakar Kushwaha ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 27541d91011SPrabhakar Kushwaha u32 porbmsr = in_be32(&gur->porbmsr); 2768bd00c94SAndy Fleming u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; 27741d91011SPrabhakar Kushwaha 27841d91011SPrabhakar Kushwaha /*Configure 1588 clock-in source from RF Card*/ 27941d91011SPrabhakar Kushwaha val = QIXIS_READ_I2C(brdcfg[5]); 28041d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[5], 28141d91011SPrabhakar Kushwaha (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK); 28241d91011SPrabhakar Kushwaha 28341d91011SPrabhakar Kushwaha if (hwconfig("uart2") && hwconfig("usb1")) { 28441d91011SPrabhakar Kushwaha printf("UART2 and USB cannot work together on the board\n"); 28541d91011SPrabhakar Kushwaha printf("Remove one from hwconfig and reset\n"); 28641d91011SPrabhakar Kushwaha } else { 28741d91011SPrabhakar Kushwaha if (hwconfig("uart2")) { 28841d91011SPrabhakar Kushwaha val = QIXIS_READ_I2C(brdcfg[5]); 28941d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[5], 29041d91011SPrabhakar Kushwaha (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2); 29141d91011SPrabhakar Kushwaha clrbits_be32(&gur->pmuxcr3, 29241d91011SPrabhakar Kushwaha MPC85xx_PMUXCR3_USB_SEL_MASK); 29341d91011SPrabhakar Kushwaha setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL); 29441d91011SPrabhakar Kushwaha } else { 29541d91011SPrabhakar Kushwaha /* By default USB should be selected. 29641d91011SPrabhakar Kushwaha * Programming FPGA to select USB. */ 29741d91011SPrabhakar Kushwaha val = QIXIS_READ_I2C(brdcfg[5]); 29841d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[5], 29941d91011SPrabhakar Kushwaha (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB); 30041d91011SPrabhakar Kushwaha } 30141d91011SPrabhakar Kushwaha 30241d91011SPrabhakar Kushwaha } 30341d91011SPrabhakar Kushwaha 30441d91011SPrabhakar Kushwaha if (hwconfig("sim")) { 30541d91011SPrabhakar Kushwaha if (romloc == PORBMSR_ROMLOC_NAND_2K || 30641d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_NOR || 30741d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_SPI) { 30841d91011SPrabhakar Kushwaha 30941d91011SPrabhakar Kushwaha val = QIXIS_READ_I2C(brdcfg[3]); 31041d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[3], val|0x10); 31141d91011SPrabhakar Kushwaha clrbits_be32(&gur->pmuxcr, 31241d91011SPrabhakar Kushwaha MPC85xx_PMUXCR0_SIM_SEL_MASK); 31341d91011SPrabhakar Kushwaha setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL); 31441d91011SPrabhakar Kushwaha } 31541d91011SPrabhakar Kushwaha } 31641d91011SPrabhakar Kushwaha 31741d91011SPrabhakar Kushwaha if (hwconfig("uart3")) { 31841d91011SPrabhakar Kushwaha if (romloc == PORBMSR_ROMLOC_NAND_2K || 31941d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_NOR || 32041d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_SDHC) { 32141d91011SPrabhakar Kushwaha 32241d91011SPrabhakar Kushwaha /* UART3 and SPI1 (Flashes) are muxed together */ 32341d91011SPrabhakar Kushwaha val = QIXIS_READ_I2C(brdcfg[3]); 32441d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3)); 32541d91011SPrabhakar Kushwaha clrbits_be32(&gur->pmuxcr3, 32641d91011SPrabhakar Kushwaha MPC85xx_PMUXCR3_UART3_SEL_MASK); 32741d91011SPrabhakar Kushwaha setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL); 32841d91011SPrabhakar Kushwaha 32941d91011SPrabhakar Kushwaha /* MUX to select UART3 connection to J24 header 33041d91011SPrabhakar Kushwaha * or to GPS */ 33141d91011SPrabhakar Kushwaha val = QIXIS_READ_I2C(brdcfg[6]); 33241d91011SPrabhakar Kushwaha if (hwconfig("gps")) 33341d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[6], 33441d91011SPrabhakar Kushwaha (val | GPS_MUX_SEL_GPS)); 33541d91011SPrabhakar Kushwaha else 33641d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[6], 33741d91011SPrabhakar Kushwaha (val & ~(GPS_MUX_SEL_GPS))); 33841d91011SPrabhakar Kushwaha } 33941d91011SPrabhakar Kushwaha } 34041d91011SPrabhakar Kushwaha return 0; 34141d91011SPrabhakar Kushwaha } 34241d91011SPrabhakar Kushwaha 34341d91011SPrabhakar Kushwaha void fdt_del_node_compat(void *blob, const char *compatible) 34441d91011SPrabhakar Kushwaha { 34541d91011SPrabhakar Kushwaha int err; 34641d91011SPrabhakar Kushwaha int off = fdt_node_offset_by_compatible(blob, -1, compatible); 34741d91011SPrabhakar Kushwaha if (off < 0) { 34841d91011SPrabhakar Kushwaha printf("WARNING: could not find compatible node %s: %s.\n", 34941d91011SPrabhakar Kushwaha compatible, fdt_strerror(off)); 35041d91011SPrabhakar Kushwaha return; 35141d91011SPrabhakar Kushwaha } 35241d91011SPrabhakar Kushwaha err = fdt_del_node(blob, off); 35341d91011SPrabhakar Kushwaha if (err < 0) { 35441d91011SPrabhakar Kushwaha printf("WARNING: could not remove %s: %s.\n", 35541d91011SPrabhakar Kushwaha compatible, fdt_strerror(err)); 35641d91011SPrabhakar Kushwaha } 35741d91011SPrabhakar Kushwaha } 35841d91011SPrabhakar Kushwaha 35941d91011SPrabhakar Kushwaha #if defined(CONFIG_OF_BOARD_SETUP) 36042a9e2feSAshish Kumar #ifdef CONFIG_FDT_FIXUP_PARTITIONS 36142a9e2feSAshish Kumar struct node_info nodes[] = { 36242a9e2feSAshish Kumar { "cfi-flash", MTD_DEV_TYPE_NOR, }, 36342a9e2feSAshish Kumar { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, }, 36442a9e2feSAshish Kumar }; 36542a9e2feSAshish Kumar #endif 366e895a4b0SSimon Glass int ft_board_setup(void *blob, bd_t *bd) 36741d91011SPrabhakar Kushwaha { 36841d91011SPrabhakar Kushwaha phys_addr_t base; 36941d91011SPrabhakar Kushwaha phys_size_t size; 37041d91011SPrabhakar Kushwaha 37141d91011SPrabhakar Kushwaha ft_cpu_setup(blob, bd); 37241d91011SPrabhakar Kushwaha 37341d91011SPrabhakar Kushwaha base = getenv_bootm_low(); 37441d91011SPrabhakar Kushwaha size = getenv_bootm_size(); 37541d91011SPrabhakar Kushwaha 37641d91011SPrabhakar Kushwaha #if defined(CONFIG_PCI) 37741d91011SPrabhakar Kushwaha FT_FSL_PCI_SETUP; 37841d91011SPrabhakar Kushwaha #endif 37941d91011SPrabhakar Kushwaha 38041d91011SPrabhakar Kushwaha fdt_fixup_memory(blob, (u64)base, (u64)size); 38142a9e2feSAshish Kumar #ifdef CONFIG_FDT_FIXUP_PARTITIONS 38242a9e2feSAshish Kumar fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); 38342a9e2feSAshish Kumar #endif 38441d91011SPrabhakar Kushwaha 38541d91011SPrabhakar Kushwaha ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 38641d91011SPrabhakar Kushwaha u32 porbmsr = in_be32(&gur->porbmsr); 3878bd00c94SAndy Fleming u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; 38841d91011SPrabhakar Kushwaha 38941d91011SPrabhakar Kushwaha if (!(hwconfig("uart2") && hwconfig("usb1"))) { 39041d91011SPrabhakar Kushwaha /* If uart2 is there in hwconfig remove usb node from 39141d91011SPrabhakar Kushwaha * device tree */ 39241d91011SPrabhakar Kushwaha 39341d91011SPrabhakar Kushwaha if (hwconfig("uart2")) { 39441d91011SPrabhakar Kushwaha /* remove dts usb node */ 39541d91011SPrabhakar Kushwaha fdt_del_node_compat(blob, "fsl-usb2-dr"); 39641d91011SPrabhakar Kushwaha } else { 397a5c289b9SSriram Dash fsl_fdt_fixup_dr_usb(blob, bd); 39841d91011SPrabhakar Kushwaha fdt_del_node_and_alias(blob, "serial2"); 39941d91011SPrabhakar Kushwaha } 40041d91011SPrabhakar Kushwaha } 40141d91011SPrabhakar Kushwaha 40241d91011SPrabhakar Kushwaha if (hwconfig("uart3")) { 40341d91011SPrabhakar Kushwaha if (romloc == PORBMSR_ROMLOC_NAND_2K || 40441d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_NOR || 40541d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_SDHC) 40641d91011SPrabhakar Kushwaha /* Delete SPI node from the device tree */ 40741d91011SPrabhakar Kushwaha fdt_del_node_and_alias(blob, "spi1"); 40841d91011SPrabhakar Kushwaha } else 40941d91011SPrabhakar Kushwaha fdt_del_node_and_alias(blob, "serial3"); 41041d91011SPrabhakar Kushwaha 41141d91011SPrabhakar Kushwaha if (hwconfig("sim")) { 41241d91011SPrabhakar Kushwaha if (romloc == PORBMSR_ROMLOC_NAND_2K || 41341d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_NOR || 41441d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_SPI) { 41541d91011SPrabhakar Kushwaha 41641d91011SPrabhakar Kushwaha /* remove dts sdhc node */ 41741d91011SPrabhakar Kushwaha fdt_del_node_compat(blob, "fsl,esdhc"); 41841d91011SPrabhakar Kushwaha } else if (romloc == PORBMSR_ROMLOC_SDHC) { 41941d91011SPrabhakar Kushwaha 42041d91011SPrabhakar Kushwaha /* remove dts sim node */ 42141d91011SPrabhakar Kushwaha fdt_del_node_compat(blob, "fsl,sim-v1.0"); 42241d91011SPrabhakar Kushwaha printf("SIM & SDHC can't work together on the board"); 42341d91011SPrabhakar Kushwaha printf("\nRemove sim from hwconfig and reset\n"); 42441d91011SPrabhakar Kushwaha } 42541d91011SPrabhakar Kushwaha } 426e895a4b0SSimon Glass 427e895a4b0SSimon Glass return 0; 42841d91011SPrabhakar Kushwaha } 42941d91011SPrabhakar Kushwaha #endif 430