141d91011SPrabhakar Kushwaha /* 241d91011SPrabhakar Kushwaha * Copyright 2013 Freescale Semiconductor, Inc. 341d91011SPrabhakar Kushwaha * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 541d91011SPrabhakar Kushwaha */ 641d91011SPrabhakar Kushwaha 741d91011SPrabhakar Kushwaha #include <common.h> 841d91011SPrabhakar Kushwaha #include <asm/processor.h> 941d91011SPrabhakar Kushwaha #include <asm/mmu.h> 1041d91011SPrabhakar Kushwaha #include <asm/cache.h> 1141d91011SPrabhakar Kushwaha #include <asm/immap_85xx.h> 1241d91011SPrabhakar Kushwaha #include <asm/io.h> 1341d91011SPrabhakar Kushwaha #include <miiphy.h> 1441d91011SPrabhakar Kushwaha #include <libfdt.h> 1541d91011SPrabhakar Kushwaha #include <fdt_support.h> 1641d91011SPrabhakar Kushwaha #include <fsl_mdio.h> 1741d91011SPrabhakar Kushwaha #include <tsec.h> 1841d91011SPrabhakar Kushwaha #include <mmc.h> 1941d91011SPrabhakar Kushwaha #include <netdev.h> 2041d91011SPrabhakar Kushwaha #include <asm/fsl_ifc.h> 2141d91011SPrabhakar Kushwaha #include <hwconfig.h> 2241d91011SPrabhakar Kushwaha #include <i2c.h> 23*5614e71bSYork Sun #include <fsl_ddr_sdram.h> 2441d91011SPrabhakar Kushwaha 2541d91011SPrabhakar Kushwaha #ifdef CONFIG_PCI 2641d91011SPrabhakar Kushwaha #include <pci.h> 2741d91011SPrabhakar Kushwaha #include <asm/fsl_pci.h> 2841d91011SPrabhakar Kushwaha #endif 2941d91011SPrabhakar Kushwaha 3041d91011SPrabhakar Kushwaha #include "../common/qixis.h" 3141d91011SPrabhakar Kushwaha DECLARE_GLOBAL_DATA_PTR; 3241d91011SPrabhakar Kushwaha 3341d91011SPrabhakar Kushwaha 3441d91011SPrabhakar Kushwaha int board_early_init_f(void) 3541d91011SPrabhakar Kushwaha { 3641d91011SPrabhakar Kushwaha struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR; 3741d91011SPrabhakar Kushwaha 3841d91011SPrabhakar Kushwaha setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); 3941d91011SPrabhakar Kushwaha 4041d91011SPrabhakar Kushwaha return 0; 4141d91011SPrabhakar Kushwaha } 4241d91011SPrabhakar Kushwaha 4341d91011SPrabhakar Kushwaha void board_config_serdes_mux(void) 4441d91011SPrabhakar Kushwaha { 4541d91011SPrabhakar Kushwaha ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 4641d91011SPrabhakar Kushwaha u32 pordevsr = in_be32(&gur->pordevsr); 4741d91011SPrabhakar Kushwaha u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 4841d91011SPrabhakar Kushwaha MPC85xx_PORDEVSR_IO_SEL_SHIFT; 4941d91011SPrabhakar Kushwaha 5041d91011SPrabhakar Kushwaha switch (srds_cfg) { 5141d91011SPrabhakar Kushwaha /* PEX(1) PEX(2) CPRI 2 CPRI 1 */ 5241d91011SPrabhakar Kushwaha case 1: 5341d91011SPrabhakar Kushwaha case 2: 5441d91011SPrabhakar Kushwaha case 3: 5541d91011SPrabhakar Kushwaha case 4: 5641d91011SPrabhakar Kushwaha case 5: 5741d91011SPrabhakar Kushwaha case 22: 5841d91011SPrabhakar Kushwaha case 23: 5941d91011SPrabhakar Kushwaha case 24: 6041d91011SPrabhakar Kushwaha case 25: 6141d91011SPrabhakar Kushwaha case 26: 6241d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[4], 0x03); 6341d91011SPrabhakar Kushwaha break; 6441d91011SPrabhakar Kushwaha 6541d91011SPrabhakar Kushwaha /* PEX(1) PEX(2) SGMII1 CPRI 1 */ 6641d91011SPrabhakar Kushwaha case 6: 6741d91011SPrabhakar Kushwaha case 7: 6841d91011SPrabhakar Kushwaha case 8: 6941d91011SPrabhakar Kushwaha case 9: 7041d91011SPrabhakar Kushwaha case 10: 7141d91011SPrabhakar Kushwaha case 27: 7241d91011SPrabhakar Kushwaha case 28: 7341d91011SPrabhakar Kushwaha case 29: 7441d91011SPrabhakar Kushwaha case 30: 7541d91011SPrabhakar Kushwaha case 31: 7641d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[4], 0x01); 7741d91011SPrabhakar Kushwaha break; 7841d91011SPrabhakar Kushwaha 7941d91011SPrabhakar Kushwaha /* PEX(1) PEX(2) SGMII1 SGMII2 */ 8041d91011SPrabhakar Kushwaha case 11: 8141d91011SPrabhakar Kushwaha case 32: 8241d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[4], 0x00); 8341d91011SPrabhakar Kushwaha break; 8441d91011SPrabhakar Kushwaha 8541d91011SPrabhakar Kushwaha /* PEX(1) SGMII2 CPRI 2 CPRI 1 */ 8641d91011SPrabhakar Kushwaha case 12: 8741d91011SPrabhakar Kushwaha case 13: 8841d91011SPrabhakar Kushwaha case 14: 8941d91011SPrabhakar Kushwaha case 15: 9041d91011SPrabhakar Kushwaha case 16: 9141d91011SPrabhakar Kushwaha case 33: 9241d91011SPrabhakar Kushwaha case 34: 9341d91011SPrabhakar Kushwaha case 35: 9441d91011SPrabhakar Kushwaha case 36: 9541d91011SPrabhakar Kushwaha case 37: 9641d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[4], 0x07); 9741d91011SPrabhakar Kushwaha break; 9841d91011SPrabhakar Kushwaha 9941d91011SPrabhakar Kushwaha /* PEX(1) SGMII2 SGMII1 CPRI 1 */ 10041d91011SPrabhakar Kushwaha case 17: 10141d91011SPrabhakar Kushwaha case 18: 10241d91011SPrabhakar Kushwaha case 19: 10341d91011SPrabhakar Kushwaha case 20: 10441d91011SPrabhakar Kushwaha case 21: 10541d91011SPrabhakar Kushwaha case 38: 10641d91011SPrabhakar Kushwaha case 39: 10741d91011SPrabhakar Kushwaha case 40: 10841d91011SPrabhakar Kushwaha case 41: 10941d91011SPrabhakar Kushwaha case 42: 11041d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[4], 0x05); 11141d91011SPrabhakar Kushwaha break; 11241d91011SPrabhakar Kushwaha 11341d91011SPrabhakar Kushwaha /* SGMII1 SGMII2 CPRI 2 CPRI 1 */ 11441d91011SPrabhakar Kushwaha case 43: 11541d91011SPrabhakar Kushwaha case 44: 11641d91011SPrabhakar Kushwaha case 45: 11741d91011SPrabhakar Kushwaha case 46: 11841d91011SPrabhakar Kushwaha case 47: 11941d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[4], 0x0F); 12041d91011SPrabhakar Kushwaha break; 12141d91011SPrabhakar Kushwaha 12241d91011SPrabhakar Kushwaha 12341d91011SPrabhakar Kushwaha default: 12441d91011SPrabhakar Kushwaha break; 12541d91011SPrabhakar Kushwaha } 12641d91011SPrabhakar Kushwaha } 12741d91011SPrabhakar Kushwaha 128f9d379a7SPriyanka Jain /* Configure DSP DDR controller */ 129f9d379a7SPriyanka Jain void dsp_ddr_configure(void) 130f9d379a7SPriyanka Jain { 131f9d379a7SPriyanka Jain /* 132f9d379a7SPriyanka Jain *There are separate DDR-controllers for DSP and PowerPC side DDR. 133f9d379a7SPriyanka Jain *copy the ddr controller settings from PowerPC side DDR controller 134f9d379a7SPriyanka Jain *to the DSP DDR controller as connected DDR memories are similar. 135f9d379a7SPriyanka Jain */ 136f9d379a7SPriyanka Jain ccsr_ddr_t __iomem *pa_ddr = 137*5614e71bSYork Sun (ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DDR_ADDR; 138f9d379a7SPriyanka Jain ccsr_ddr_t temp_ddr; 139f9d379a7SPriyanka Jain ccsr_ddr_t __iomem *dsp_ddr = 140f9d379a7SPriyanka Jain (ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR; 141f9d379a7SPriyanka Jain 142f9d379a7SPriyanka Jain memcpy(&temp_ddr, pa_ddr, sizeof(ccsr_ddr_t)); 143f9d379a7SPriyanka Jain temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS; 144f9d379a7SPriyanka Jain temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN; 145f9d379a7SPriyanka Jain memcpy(dsp_ddr, &temp_ddr, sizeof(ccsr_ddr_t)); 146f9d379a7SPriyanka Jain dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN; 147f9d379a7SPriyanka Jain } 148f9d379a7SPriyanka Jain 14941d91011SPrabhakar Kushwaha int board_early_init_r(void) 15041d91011SPrabhakar Kushwaha { 15141d91011SPrabhakar Kushwaha #ifndef CONFIG_SYS_NO_FLASH 15241d91011SPrabhakar Kushwaha const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 15341d91011SPrabhakar Kushwaha const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 15441d91011SPrabhakar Kushwaha 15541d91011SPrabhakar Kushwaha /* 15641d91011SPrabhakar Kushwaha * Remap Boot flash region to caching-inhibited 15741d91011SPrabhakar Kushwaha * so that flash can be erased properly. 15841d91011SPrabhakar Kushwaha */ 15941d91011SPrabhakar Kushwaha 16041d91011SPrabhakar Kushwaha /* Flush d-cache and invalidate i-cache of any FLASH data */ 16141d91011SPrabhakar Kushwaha flush_dcache(); 16241d91011SPrabhakar Kushwaha invalidate_icache(); 16341d91011SPrabhakar Kushwaha 16441d91011SPrabhakar Kushwaha /* invalidate existing TLB entry for flash */ 16541d91011SPrabhakar Kushwaha disable_tlb(flash_esel); 16641d91011SPrabhakar Kushwaha 16741d91011SPrabhakar Kushwaha set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 16841d91011SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 16941d91011SPrabhakar Kushwaha 0, flash_esel, BOOKE_PAGESZ_64M, 1); 17041d91011SPrabhakar Kushwaha 17141d91011SPrabhakar Kushwaha set_tlb(1, flashbase + 0x4000000, 17241d91011SPrabhakar Kushwaha CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000, 17341d91011SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 17441d91011SPrabhakar Kushwaha 0, flash_esel+1, BOOKE_PAGESZ_64M, 1); 17541d91011SPrabhakar Kushwaha #endif 17641d91011SPrabhakar Kushwaha board_config_serdes_mux(); 177f9d379a7SPriyanka Jain dsp_ddr_configure(); 17841d91011SPrabhakar Kushwaha return 0; 17941d91011SPrabhakar Kushwaha } 18041d91011SPrabhakar Kushwaha 18141d91011SPrabhakar Kushwaha #ifdef CONFIG_PCI 18241d91011SPrabhakar Kushwaha void pci_init_board(void) 18341d91011SPrabhakar Kushwaha { 18441d91011SPrabhakar Kushwaha fsl_pcie_init_board(0); 18541d91011SPrabhakar Kushwaha } 18641d91011SPrabhakar Kushwaha #endif /* ifdef CONFIG_PCI */ 18741d91011SPrabhakar Kushwaha 18841d91011SPrabhakar Kushwaha int checkboard(void) 18941d91011SPrabhakar Kushwaha { 19041d91011SPrabhakar Kushwaha struct cpu_type *cpu; 19141d91011SPrabhakar Kushwaha u8 sw; 19241d91011SPrabhakar Kushwaha 19367ac13b1SSimon Glass cpu = gd->arch.cpu; 19441d91011SPrabhakar Kushwaha printf("Board: %sQDS\n", cpu->name); 19541d91011SPrabhakar Kushwaha 19641d91011SPrabhakar Kushwaha printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n", 19741d91011SPrabhakar Kushwaha QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver)); 19841d91011SPrabhakar Kushwaha 19941d91011SPrabhakar Kushwaha sw = QIXIS_READ(brdcfg[0]); 20041d91011SPrabhakar Kushwaha sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 20141d91011SPrabhakar Kushwaha 20241d91011SPrabhakar Kushwaha printf("IFC chip select:"); 20341d91011SPrabhakar Kushwaha switch (sw) { 20441d91011SPrabhakar Kushwaha case 0: 20541d91011SPrabhakar Kushwaha printf("NOR\n"); 20641d91011SPrabhakar Kushwaha break; 20741d91011SPrabhakar Kushwaha case 2: 20841d91011SPrabhakar Kushwaha printf("Promjet\n"); 20941d91011SPrabhakar Kushwaha break; 21041d91011SPrabhakar Kushwaha case 4: 21141d91011SPrabhakar Kushwaha printf("NAND\n"); 21241d91011SPrabhakar Kushwaha break; 21341d91011SPrabhakar Kushwaha default: 21441d91011SPrabhakar Kushwaha printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 21541d91011SPrabhakar Kushwaha break; 21641d91011SPrabhakar Kushwaha } 21741d91011SPrabhakar Kushwaha 21841d91011SPrabhakar Kushwaha return 0; 21941d91011SPrabhakar Kushwaha } 22041d91011SPrabhakar Kushwaha 22141d91011SPrabhakar Kushwaha #ifdef CONFIG_TSEC_ENET 22241d91011SPrabhakar Kushwaha int board_eth_init(bd_t *bis) 22341d91011SPrabhakar Kushwaha { 22441d91011SPrabhakar Kushwaha struct fsl_pq_mdio_info mdio_info; 22541d91011SPrabhakar Kushwaha struct tsec_info_struct tsec_info[4]; 22641d91011SPrabhakar Kushwaha int num = 0; 22741d91011SPrabhakar Kushwaha 22841d91011SPrabhakar Kushwaha #ifdef CONFIG_TSEC1 22941d91011SPrabhakar Kushwaha SET_STD_TSEC_INFO(tsec_info[num], 1); 23041d91011SPrabhakar Kushwaha num++; 23141d91011SPrabhakar Kushwaha 23241d91011SPrabhakar Kushwaha #endif 23341d91011SPrabhakar Kushwaha 23441d91011SPrabhakar Kushwaha #ifdef CONFIG_TSEC2 23541d91011SPrabhakar Kushwaha SET_STD_TSEC_INFO(tsec_info[num], 2); 23641d91011SPrabhakar Kushwaha num++; 23741d91011SPrabhakar Kushwaha #endif 23841d91011SPrabhakar Kushwaha 23941d91011SPrabhakar Kushwaha mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 24041d91011SPrabhakar Kushwaha mdio_info.name = DEFAULT_MII_NAME; 24141d91011SPrabhakar Kushwaha 24241d91011SPrabhakar Kushwaha fsl_pq_mdio_init(bis, &mdio_info); 24341d91011SPrabhakar Kushwaha tsec_eth_init(bis, tsec_info, num); 24441d91011SPrabhakar Kushwaha 24541d91011SPrabhakar Kushwaha #ifdef CONFIG_PCI 24641d91011SPrabhakar Kushwaha pci_eth_init(bis); 24741d91011SPrabhakar Kushwaha #endif 24841d91011SPrabhakar Kushwaha 24941d91011SPrabhakar Kushwaha return 0; 25041d91011SPrabhakar Kushwaha } 25141d91011SPrabhakar Kushwaha #endif 25241d91011SPrabhakar Kushwaha 25341d91011SPrabhakar Kushwaha #define USBMUX_SEL_MASK 0xc0 25441d91011SPrabhakar Kushwaha #define USBMUX_SEL_UART2 0xc0 25541d91011SPrabhakar Kushwaha #define USBMUX_SEL_USB 0x40 25641d91011SPrabhakar Kushwaha #define SPIMUX_SEL_UART3 0x80 25741d91011SPrabhakar Kushwaha #define GPS_MUX_SEL_GPS 0x40 25841d91011SPrabhakar Kushwaha 25941d91011SPrabhakar Kushwaha #define TSEC_1588_CLKIN_MASK 0x03 26041d91011SPrabhakar Kushwaha #define CON_XCVR_REF_CLK 0x00 26141d91011SPrabhakar Kushwaha 26241d91011SPrabhakar Kushwaha int misc_init_r(void) 26341d91011SPrabhakar Kushwaha { 26441d91011SPrabhakar Kushwaha u8 val; 26541d91011SPrabhakar Kushwaha ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 26641d91011SPrabhakar Kushwaha u32 porbmsr = in_be32(&gur->porbmsr); 2678bd00c94SAndy Fleming u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; 26841d91011SPrabhakar Kushwaha 26941d91011SPrabhakar Kushwaha /*Configure 1588 clock-in source from RF Card*/ 27041d91011SPrabhakar Kushwaha val = QIXIS_READ_I2C(brdcfg[5]); 27141d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[5], 27241d91011SPrabhakar Kushwaha (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK); 27341d91011SPrabhakar Kushwaha 27441d91011SPrabhakar Kushwaha if (hwconfig("uart2") && hwconfig("usb1")) { 27541d91011SPrabhakar Kushwaha printf("UART2 and USB cannot work together on the board\n"); 27641d91011SPrabhakar Kushwaha printf("Remove one from hwconfig and reset\n"); 27741d91011SPrabhakar Kushwaha } else { 27841d91011SPrabhakar Kushwaha if (hwconfig("uart2")) { 27941d91011SPrabhakar Kushwaha val = QIXIS_READ_I2C(brdcfg[5]); 28041d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[5], 28141d91011SPrabhakar Kushwaha (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2); 28241d91011SPrabhakar Kushwaha clrbits_be32(&gur->pmuxcr3, 28341d91011SPrabhakar Kushwaha MPC85xx_PMUXCR3_USB_SEL_MASK); 28441d91011SPrabhakar Kushwaha setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL); 28541d91011SPrabhakar Kushwaha } else { 28641d91011SPrabhakar Kushwaha /* By default USB should be selected. 28741d91011SPrabhakar Kushwaha * Programming FPGA to select USB. */ 28841d91011SPrabhakar Kushwaha val = QIXIS_READ_I2C(brdcfg[5]); 28941d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[5], 29041d91011SPrabhakar Kushwaha (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB); 29141d91011SPrabhakar Kushwaha } 29241d91011SPrabhakar Kushwaha 29341d91011SPrabhakar Kushwaha } 29441d91011SPrabhakar Kushwaha 29541d91011SPrabhakar Kushwaha if (hwconfig("sim")) { 29641d91011SPrabhakar Kushwaha if (romloc == PORBMSR_ROMLOC_NAND_2K || 29741d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_NOR || 29841d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_SPI) { 29941d91011SPrabhakar Kushwaha 30041d91011SPrabhakar Kushwaha val = QIXIS_READ_I2C(brdcfg[3]); 30141d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[3], val|0x10); 30241d91011SPrabhakar Kushwaha clrbits_be32(&gur->pmuxcr, 30341d91011SPrabhakar Kushwaha MPC85xx_PMUXCR0_SIM_SEL_MASK); 30441d91011SPrabhakar Kushwaha setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL); 30541d91011SPrabhakar Kushwaha } 30641d91011SPrabhakar Kushwaha } 30741d91011SPrabhakar Kushwaha 30841d91011SPrabhakar Kushwaha if (hwconfig("uart3")) { 30941d91011SPrabhakar Kushwaha if (romloc == PORBMSR_ROMLOC_NAND_2K || 31041d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_NOR || 31141d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_SDHC) { 31241d91011SPrabhakar Kushwaha 31341d91011SPrabhakar Kushwaha /* UART3 and SPI1 (Flashes) are muxed together */ 31441d91011SPrabhakar Kushwaha val = QIXIS_READ_I2C(brdcfg[3]); 31541d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3)); 31641d91011SPrabhakar Kushwaha clrbits_be32(&gur->pmuxcr3, 31741d91011SPrabhakar Kushwaha MPC85xx_PMUXCR3_UART3_SEL_MASK); 31841d91011SPrabhakar Kushwaha setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL); 31941d91011SPrabhakar Kushwaha 32041d91011SPrabhakar Kushwaha /* MUX to select UART3 connection to J24 header 32141d91011SPrabhakar Kushwaha * or to GPS */ 32241d91011SPrabhakar Kushwaha val = QIXIS_READ_I2C(brdcfg[6]); 32341d91011SPrabhakar Kushwaha if (hwconfig("gps")) 32441d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[6], 32541d91011SPrabhakar Kushwaha (val | GPS_MUX_SEL_GPS)); 32641d91011SPrabhakar Kushwaha else 32741d91011SPrabhakar Kushwaha QIXIS_WRITE_I2C(brdcfg[6], 32841d91011SPrabhakar Kushwaha (val & ~(GPS_MUX_SEL_GPS))); 32941d91011SPrabhakar Kushwaha } 33041d91011SPrabhakar Kushwaha } 33141d91011SPrabhakar Kushwaha return 0; 33241d91011SPrabhakar Kushwaha } 33341d91011SPrabhakar Kushwaha 33441d91011SPrabhakar Kushwaha void fdt_del_node_compat(void *blob, const char *compatible) 33541d91011SPrabhakar Kushwaha { 33641d91011SPrabhakar Kushwaha int err; 33741d91011SPrabhakar Kushwaha int off = fdt_node_offset_by_compatible(blob, -1, compatible); 33841d91011SPrabhakar Kushwaha if (off < 0) { 33941d91011SPrabhakar Kushwaha printf("WARNING: could not find compatible node %s: %s.\n", 34041d91011SPrabhakar Kushwaha compatible, fdt_strerror(off)); 34141d91011SPrabhakar Kushwaha return; 34241d91011SPrabhakar Kushwaha } 34341d91011SPrabhakar Kushwaha err = fdt_del_node(blob, off); 34441d91011SPrabhakar Kushwaha if (err < 0) { 34541d91011SPrabhakar Kushwaha printf("WARNING: could not remove %s: %s.\n", 34641d91011SPrabhakar Kushwaha compatible, fdt_strerror(err)); 34741d91011SPrabhakar Kushwaha } 34841d91011SPrabhakar Kushwaha } 34941d91011SPrabhakar Kushwaha 35041d91011SPrabhakar Kushwaha #if defined(CONFIG_OF_BOARD_SETUP) 35141d91011SPrabhakar Kushwaha void ft_board_setup(void *blob, bd_t *bd) 35241d91011SPrabhakar Kushwaha { 35341d91011SPrabhakar Kushwaha phys_addr_t base; 35441d91011SPrabhakar Kushwaha phys_size_t size; 35541d91011SPrabhakar Kushwaha 35641d91011SPrabhakar Kushwaha ft_cpu_setup(blob, bd); 35741d91011SPrabhakar Kushwaha 35841d91011SPrabhakar Kushwaha base = getenv_bootm_low(); 35941d91011SPrabhakar Kushwaha size = getenv_bootm_size(); 36041d91011SPrabhakar Kushwaha 36141d91011SPrabhakar Kushwaha #if defined(CONFIG_PCI) 36241d91011SPrabhakar Kushwaha FT_FSL_PCI_SETUP; 36341d91011SPrabhakar Kushwaha #endif 36441d91011SPrabhakar Kushwaha 36541d91011SPrabhakar Kushwaha fdt_fixup_memory(blob, (u64)base, (u64)size); 36641d91011SPrabhakar Kushwaha 36741d91011SPrabhakar Kushwaha ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 36841d91011SPrabhakar Kushwaha u32 porbmsr = in_be32(&gur->porbmsr); 3698bd00c94SAndy Fleming u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; 37041d91011SPrabhakar Kushwaha 37141d91011SPrabhakar Kushwaha if (!(hwconfig("uart2") && hwconfig("usb1"))) { 37241d91011SPrabhakar Kushwaha /* If uart2 is there in hwconfig remove usb node from 37341d91011SPrabhakar Kushwaha * device tree */ 37441d91011SPrabhakar Kushwaha 37541d91011SPrabhakar Kushwaha if (hwconfig("uart2")) { 37641d91011SPrabhakar Kushwaha /* remove dts usb node */ 37741d91011SPrabhakar Kushwaha fdt_del_node_compat(blob, "fsl-usb2-dr"); 37841d91011SPrabhakar Kushwaha } else { 37941d91011SPrabhakar Kushwaha fdt_fixup_dr_usb(blob, bd); 38041d91011SPrabhakar Kushwaha fdt_del_node_and_alias(blob, "serial2"); 38141d91011SPrabhakar Kushwaha } 38241d91011SPrabhakar Kushwaha } 38341d91011SPrabhakar Kushwaha 38441d91011SPrabhakar Kushwaha if (hwconfig("uart3")) { 38541d91011SPrabhakar Kushwaha if (romloc == PORBMSR_ROMLOC_NAND_2K || 38641d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_NOR || 38741d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_SDHC) 38841d91011SPrabhakar Kushwaha /* Delete SPI node from the device tree */ 38941d91011SPrabhakar Kushwaha fdt_del_node_and_alias(blob, "spi1"); 39041d91011SPrabhakar Kushwaha } else 39141d91011SPrabhakar Kushwaha fdt_del_node_and_alias(blob, "serial3"); 39241d91011SPrabhakar Kushwaha 39341d91011SPrabhakar Kushwaha if (hwconfig("sim")) { 39441d91011SPrabhakar Kushwaha if (romloc == PORBMSR_ROMLOC_NAND_2K || 39541d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_NOR || 39641d91011SPrabhakar Kushwaha romloc == PORBMSR_ROMLOC_SPI) { 39741d91011SPrabhakar Kushwaha 39841d91011SPrabhakar Kushwaha /* remove dts sdhc node */ 39941d91011SPrabhakar Kushwaha fdt_del_node_compat(blob, "fsl,esdhc"); 40041d91011SPrabhakar Kushwaha } else if (romloc == PORBMSR_ROMLOC_SDHC) { 40141d91011SPrabhakar Kushwaha 40241d91011SPrabhakar Kushwaha /* remove dts sim node */ 40341d91011SPrabhakar Kushwaha fdt_del_node_compat(blob, "fsl,sim-v1.0"); 40441d91011SPrabhakar Kushwaha printf("SIM & SDHC can't work together on the board"); 40541d91011SPrabhakar Kushwaha printf("\nRemove sim from hwconfig and reset\n"); 40641d91011SPrabhakar Kushwaha } 40741d91011SPrabhakar Kushwaha } 40841d91011SPrabhakar Kushwaha } 40941d91011SPrabhakar Kushwaha #endif 410