17530d341SPrabhakar Kushwaha /* 27530d341SPrabhakar Kushwaha * Copyright 2011-2012 Freescale Semiconductor, Inc. 37530d341SPrabhakar Kushwaha * 4*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 57530d341SPrabhakar Kushwaha */ 67530d341SPrabhakar Kushwaha 77530d341SPrabhakar Kushwaha #include <common.h> 87530d341SPrabhakar Kushwaha #include <asm/mmu.h> 97530d341SPrabhakar Kushwaha 107530d341SPrabhakar Kushwaha struct fsl_e_tlb_entry tlb_table[] = { 117530d341SPrabhakar Kushwaha /* TLB 0 - for temp stack in cache */ 127530d341SPrabhakar Kushwaha SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 137530d341SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, 0, 147530d341SPrabhakar Kushwaha 0, 0, BOOKE_PAGESZ_4K, 0), 157530d341SPrabhakar Kushwaha SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 167530d341SPrabhakar Kushwaha CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 177530d341SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, 0, 187530d341SPrabhakar Kushwaha 0, 0, BOOKE_PAGESZ_4K, 0), 197530d341SPrabhakar Kushwaha SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 207530d341SPrabhakar Kushwaha CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 217530d341SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, 0, 227530d341SPrabhakar Kushwaha 0, 0, BOOKE_PAGESZ_4K, 0), 237530d341SPrabhakar Kushwaha SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 247530d341SPrabhakar Kushwaha CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 257530d341SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, 0, 267530d341SPrabhakar Kushwaha 0, 0, BOOKE_PAGESZ_4K, 0), 277530d341SPrabhakar Kushwaha 287530d341SPrabhakar Kushwaha /* TLB 1 */ 297530d341SPrabhakar Kushwaha /* *I*** - Covers boot page */ 30f64bd7c0SPrabhakar Kushwaha SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 31f64bd7c0SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 32f64bd7c0SPrabhakar Kushwaha 0, 0, BOOKE_PAGESZ_4K, 1), 33f64bd7c0SPrabhakar Kushwaha #ifdef CONFIG_SPL_NAND_MINIMAL 34f1593269SPrabhakar Kushwaha SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, 357530d341SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 36f64bd7c0SPrabhakar Kushwaha 0, 10, BOOKE_PAGESZ_4K, 1), 37f64bd7c0SPrabhakar Kushwaha #endif 387530d341SPrabhakar Kushwaha 397530d341SPrabhakar Kushwaha /* *I*G* - CCSRBAR (PA) */ 407530d341SPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 417530d341SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 427530d341SPrabhakar Kushwaha 0, 1, BOOKE_PAGESZ_1M, 1), 437530d341SPrabhakar Kushwaha 44765b0bdbSPriyanka Jain /* CCSRBAR (DSP) */ 45765b0bdbSPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR, 46765b0bdbSPriyanka Jain CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, 47765b0bdbSPriyanka Jain MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 48765b0bdbSPriyanka Jain 0, 2, BOOKE_PAGESZ_1M, 1), 49765b0bdbSPriyanka Jain 50f1593269SPrabhakar Kushwaha #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) 517530d341SPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 527530d341SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, 0, 537530d341SPrabhakar Kushwaha 0, 8, BOOKE_PAGESZ_1G, 1), 547530d341SPrabhakar Kushwaha #endif 557530d341SPrabhakar Kushwaha 567530d341SPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 577530d341SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 587530d341SPrabhakar Kushwaha 0, 3, BOOKE_PAGESZ_1M, 1) 597530d341SPrabhakar Kushwaha 607530d341SPrabhakar Kushwaha }; 617530d341SPrabhakar Kushwaha 627530d341SPrabhakar Kushwaha int num_tlb_entries = ARRAY_SIZE(tlb_table); 63