1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 27530d341SPrabhakar Kushwaha /* 37530d341SPrabhakar Kushwaha * Copyright 2011-2012 Freescale Semiconductor, Inc. 47530d341SPrabhakar Kushwaha */ 57530d341SPrabhakar Kushwaha 67530d341SPrabhakar Kushwaha #include <common.h> 77530d341SPrabhakar Kushwaha #include <asm/mmu.h> 87530d341SPrabhakar Kushwaha 97530d341SPrabhakar Kushwaha struct fsl_e_tlb_entry tlb_table[] = { 107530d341SPrabhakar Kushwaha /* TLB 0 - for temp stack in cache */ 117530d341SPrabhakar Kushwaha SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 127530d341SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, 0, 137530d341SPrabhakar Kushwaha 0, 0, BOOKE_PAGESZ_4K, 0), 147530d341SPrabhakar Kushwaha SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 157530d341SPrabhakar Kushwaha CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 167530d341SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, 0, 177530d341SPrabhakar Kushwaha 0, 0, BOOKE_PAGESZ_4K, 0), 187530d341SPrabhakar Kushwaha SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 197530d341SPrabhakar Kushwaha CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 207530d341SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, 0, 217530d341SPrabhakar Kushwaha 0, 0, BOOKE_PAGESZ_4K, 0), 227530d341SPrabhakar Kushwaha SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 237530d341SPrabhakar Kushwaha CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 247530d341SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, 0, 257530d341SPrabhakar Kushwaha 0, 0, BOOKE_PAGESZ_4K, 0), 267530d341SPrabhakar Kushwaha 277530d341SPrabhakar Kushwaha /* TLB 1 */ 287530d341SPrabhakar Kushwaha /* *I*** - Covers boot page */ 29f64bd7c0SPrabhakar Kushwaha SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 30f64bd7c0SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 31f64bd7c0SPrabhakar Kushwaha 0, 0, BOOKE_PAGESZ_4K, 1), 32fbe76ae4SPrabhakar Kushwaha #ifdef CONFIG_SPL_NAND_BOOT 33f1593269SPrabhakar Kushwaha SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, 347530d341SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 35f64bd7c0SPrabhakar Kushwaha 0, 10, BOOKE_PAGESZ_4K, 1), 36f64bd7c0SPrabhakar Kushwaha #endif 377530d341SPrabhakar Kushwaha 387530d341SPrabhakar Kushwaha /* *I*G* - CCSRBAR (PA) */ 397530d341SPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 407530d341SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 417530d341SPrabhakar Kushwaha 0, 1, BOOKE_PAGESZ_1M, 1), 427530d341SPrabhakar Kushwaha 43765b0bdbSPriyanka Jain /* CCSRBAR (DSP) */ 44765b0bdbSPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR, 45765b0bdbSPriyanka Jain CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, 46765b0bdbSPriyanka Jain MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 47765b0bdbSPriyanka Jain 0, 2, BOOKE_PAGESZ_1M, 1), 48765b0bdbSPriyanka Jain 49f1593269SPrabhakar Kushwaha #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) 507530d341SPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 51316f0d0fSYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 527530d341SPrabhakar Kushwaha 0, 8, BOOKE_PAGESZ_1G, 1), 537530d341SPrabhakar Kushwaha #endif 547530d341SPrabhakar Kushwaha 557530d341SPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 567530d341SPrabhakar Kushwaha MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 577530d341SPrabhakar Kushwaha 0, 3, BOOKE_PAGESZ_1M, 1) 587530d341SPrabhakar Kushwaha 597530d341SPrabhakar Kushwaha }; 607530d341SPrabhakar Kushwaha 617530d341SPrabhakar Kushwaha int num_tlb_entries = ARRAY_SIZE(tlb_table); 62