1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <ns16550.h> 9 #include <asm/io.h> 10 #include <nand.h> 11 #include <linux/compiler.h> 12 #include <asm/fsl_law.h> 13 #include <fsl_ddr_sdram.h> 14 #include <asm/global_data.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 /* 19 * Fixed sdram init -- doesn't use serial presence detect. 20 */ 21 static void sdram_init(void) 22 { 23 struct ccsr_ddr __iomem *ddr = 24 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; 25 26 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); 27 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); 28 #if CONFIG_CHIP_SELECTS_PER_CTRL > 1 29 __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); 30 __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); 31 #endif 32 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); 33 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); 34 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); 35 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); 36 37 __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); 38 __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); 39 __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); 40 41 __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); 42 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); 43 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); 44 45 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); 46 __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); 47 __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); 48 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); 49 50 /* Set, but do not enable the memory */ 51 __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg); 52 53 asm volatile("sync;isync"); 54 udelay(500); 55 56 /* Let the controller go */ 57 out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); 58 59 set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1); 60 } 61 62 void board_init_f(ulong bootflag) 63 { 64 u32 plat_ratio; 65 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 66 67 /* initialize selected port with appropriate baud rate */ 68 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; 69 plat_ratio >>= 1; 70 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; 71 72 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 73 gd->bus_clk / 16 / CONFIG_BAUDRATE); 74 75 puts("\nNAND boot... "); 76 77 /* Initialize the DDR3 */ 78 sdram_init(); 79 80 /* copy code to RAM and jump to it - this should not return */ 81 /* NOTE - code has to be copied out of NAND buffer before 82 * other blocks can be read. 83 */ 84 relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); 85 } 86 87 void board_init_r(gd_t *gd, ulong dest_addr) 88 { 89 nand_boot(); 90 } 91 92 void putc(char c) 93 { 94 if (c == '\n') 95 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); 96 97 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); 98 } 99 100 void puts(const char *str) 101 { 102 while (*str) 103 putc(*str++); 104 } 105