1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/mmu.h> 25 #include <asm/immap_85xx.h> 26 #include <asm/processor.h> 27 #include <asm/fsl_ddr_sdram.h> 28 #include <asm/fsl_ddr_dimm_params.h> 29 #include <asm/io.h> 30 #include <asm/fsl_law.h> 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 #ifndef CONFIG_SYS_DDR_RAW_TIMING 35 #define CONFIG_SYS_DRAM_SIZE 1024 36 37 fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { 38 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, 39 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, 40 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, 41 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, 42 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, 43 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, 44 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, 45 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, 46 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, 47 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, 48 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, 49 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, 50 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, 51 .ddr_data_init = CONFIG_MEM_INIT_VALUE, 52 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, 53 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, 54 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, 55 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, 56 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, 57 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, 58 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800, 59 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, 60 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, 61 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 62 }; 63 64 fixed_ddr_parm_t fixed_ddr_parm_0[] = { 65 {750, 850, &ddr_cfg_regs_800}, 66 {0, 0, NULL} 67 }; 68 69 unsigned long get_sdram_size(void) 70 { 71 return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE); 72 } 73 74 /* 75 * Fixed sdram init -- doesn't use serial presence detect. 76 */ 77 phys_size_t fixed_sdram(void) 78 { 79 int i; 80 char buf[32]; 81 fsl_ddr_cfg_regs_t ddr_cfg_regs; 82 phys_size_t ddr_size; 83 ulong ddr_freq, ddr_freq_mhz; 84 85 ddr_freq = get_ddr_freq(0); 86 ddr_freq_mhz = ddr_freq / 1000000; 87 88 printf("Configuring DDR for %s MT/s data rate\n", 89 strmhz(buf, ddr_freq)); 90 91 for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { 92 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && 93 (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { 94 memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, 95 sizeof(ddr_cfg_regs)); 96 break; 97 } 98 } 99 100 if (fixed_ddr_parm_0[i].max_freq == 0) { 101 panic("Unsupported DDR data rate %s MT/s data rate\n", 102 strmhz(buf, ddr_freq)); 103 } 104 105 ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; 106 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); 107 108 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, 109 LAW_TRGT_IF_DDR_1) < 0) { 110 printf("ERROR setting Local Access Windows for DDR\n"); 111 return 0; 112 } 113 114 return ddr_size; 115 } 116 117 #else /* CONFIG_SYS_DDR_RAW_TIMING */ 118 /* Micron MT41J256M8HX-15E */ 119 dimm_params_t ddr_raw_timing = { 120 .n_ranks = 1, 121 .rank_density = 1073741824u, 122 .capacity = 1073741824u, 123 .primary_sdram_width = 32, 124 .ec_sdram_width = 0, 125 .registered_dimm = 0, 126 .mirrored_dimm = 0, 127 .n_row_addr = 15, 128 .n_col_addr = 10, 129 .n_banks_per_sdram_device = 8, 130 .edc_config = 0, 131 .burst_lengths_bitmask = 0x0c, 132 133 .tCKmin_X_ps = 1870, 134 .caslat_X = 0x1e << 4, /* 5,6,7,8 */ 135 .tAA_ps = 13125, 136 .tWR_ps = 15000, 137 .tRCD_ps = 13125, 138 .tRRD_ps = 7500, 139 .tRP_ps = 13125, 140 .tRAS_ps = 37500, 141 .tRC_ps = 50625, 142 .tRFC_ps = 160000, 143 .tWTR_ps = 7500, 144 .tRTP_ps = 7500, 145 .refresh_rate_ps = 7800000, 146 .tFAW_ps = 37500, 147 }; 148 149 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 150 unsigned int controller_number, 151 unsigned int dimm_number) 152 { 153 const char dimm_model[] = "Fixed DDR on board"; 154 155 if ((controller_number == 0) && (dimm_number == 0)) { 156 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 157 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 158 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 159 } 160 161 return 0; 162 } 163 164 void fsl_ddr_board_options(memctl_options_t *popts, 165 dimm_params_t *pdimm, 166 unsigned int ctrl_num) 167 { 168 int i; 169 popts->clk_adjust = 6; 170 popts->cpo_override = 0x1f; 171 popts->write_data_delay = 2; 172 popts->half_strength_driver_enable = 1; 173 /* Write leveling override */ 174 popts->wrlvl_en = 1; 175 popts->wrlvl_override = 1; 176 popts->wrlvl_sample = 0xf; 177 popts->wrlvl_start = 0x8; 178 popts->trwt_override = 1; 179 popts->trwt = 0; 180 181 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 182 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; 183 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; 184 } 185 } 186 187 #endif /* CONFIG_SYS_DDR_RAW_TIMING */ 188