1 /*
2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <asm/processor.h>
9 #include <asm/mmu.h>
10 #include <asm/cache.h>
11 #include <asm/immap_85xx.h>
12 #include <asm/io.h>
13 #include <miiphy.h>
14 #include <libfdt.h>
15 #include <fdt_support.h>
16 #include <fsl_mdio.h>
17 #include <tsec.h>
18 #include <jffs2/load_kernel.h>
19 #include <mtd_node.h>
20 #include <flash.h>
21 #include <netdev.h>
22 
23 
24 DECLARE_GLOBAL_DATA_PTR;
25 
26 int board_early_init_f(void)
27 {
28 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
29 
30 	clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42);
31 	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS);
32 
33 	clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43);
34 	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK |
35 			MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD);
36 	setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0);
37 	clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK |
38 			MPC85xx_PMUXCR_IFC_AD17_GPO_MASK,
39 			MPC85xx_PMUXCR_IFC_AD_GPIO |
40 			MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM);
41 
42 	return 0;
43 }
44 
45 int checkboard(void)
46 {
47 	struct cpu_type *cpu;
48 
49 	cpu = gd->arch.cpu;
50 	printf("Board: %sRDB\n", cpu->name);
51 
52 	return 0;
53 }
54 
55 #if defined(CONFIG_OF_BOARD_SETUP)
56 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
57 struct node_info nodes[] = {
58 	{ "fsl,ifc-nand",		MTD_DEV_TYPE_NAND, },
59 };
60 #endif
61 int ft_board_setup(void *blob, bd_t *bd)
62 {
63 	phys_addr_t base;
64 	phys_size_t size;
65 
66 	ft_cpu_setup(blob, bd);
67 
68 	base = getenv_bootm_low();
69 	size = getenv_bootm_size();
70 
71 	fdt_fixup_memory(blob, (u64)base, (u64)size);
72 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
73 	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
74 #endif
75 
76 	fsl_fdt_fixup_dr_usb(blob, bd);
77 
78 	return 0;
79 }
80 #endif
81