1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/mmu.h> 9 10 struct fsl_e_tlb_entry tlb_table[] = { 11 /* TLB 0 - for temp stack in cache */ 12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 13 CONFIG_SYS_INIT_RAM_ADDR_PHYS, 14 MAS3_SX|MAS3_SW|MAS3_SR, 0, 15 0, 0, BOOKE_PAGESZ_4K, 0), 16 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 17 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 18 MAS3_SX|MAS3_SW|MAS3_SR, 0, 19 0, 0, BOOKE_PAGESZ_4K, 0), 20 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 21 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 22 MAS3_SX|MAS3_SW|MAS3_SR, 0, 23 0, 0, BOOKE_PAGESZ_4K, 0), 24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 26 MAS3_SX|MAS3_SW|MAS3_SR, 0, 27 0, 0, BOOKE_PAGESZ_4K, 0), 28 29 /* TLB 1 */ 30 /* *I*** - Covers boot page */ 31 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 32 /* 33 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 34 * SRAM is at 0xfff00000, it covered the 0xfffff000. 35 */ 36 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 37 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 38 0, 0, BOOKE_PAGESZ_1M, 1), 39 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 40 /* 41 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the 42 * space is at 0xfff00000, it covered the 0xfffff000. 43 */ 44 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, 45 CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, 46 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 47 0, 0, BOOKE_PAGESZ_1M, 1), 48 #else 49 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 50 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 51 0, 0, BOOKE_PAGESZ_4K, 1), 52 #endif 53 54 /* *I*G* - CCSRBAR */ 55 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 56 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57 0, 1, BOOKE_PAGESZ_16M, 1), 58 59 /* *I*G* - Flash, localbus */ 60 /* This will be changed to *I*G* after relocation to RAM. */ 61 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 62 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 63 0, 2, BOOKE_PAGESZ_256M, 1), 64 65 #ifndef CONFIG_SPL_BUILD 66 /* *I*G* - PCI */ 67 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 68 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 69 0, 3, BOOKE_PAGESZ_256M, 1), 70 71 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000, 72 CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000, 73 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 74 0, 4, BOOKE_PAGESZ_256M, 1), 75 76 /* *I*G* - PCI I/O */ 77 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 78 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 79 0, 5, BOOKE_PAGESZ_64K, 1), 80 81 /* Bman/Qman */ 82 #ifdef CONFIG_SYS_BMAN_MEM_PHYS 83 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 84 MAS3_SX|MAS3_SW|MAS3_SR, 0, 85 0, 6, BOOKE_PAGESZ_16M, 1), 86 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 87 CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 88 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 89 0, 7, BOOKE_PAGESZ_16M, 1), 90 #endif 91 #ifdef CONFIG_SYS_QMAN_MEM_PHYS 92 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 93 MAS3_SX|MAS3_SW|MAS3_SR, 0, 94 0, 8, BOOKE_PAGESZ_16M, 1), 95 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 96 CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 97 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 98 0, 9, BOOKE_PAGESZ_16M, 1), 99 #endif 100 #endif 101 #ifdef CONFIG_SYS_DCSRBAR_PHYS 102 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 103 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 104 0, 10, BOOKE_PAGESZ_32M, 1), 105 #endif 106 #ifdef CONFIG_SYS_NAND_BASE 107 /* 108 * *I*G - NAND 109 */ 110 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 111 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 112 0, 11, BOOKE_PAGESZ_64K, 1), 113 #endif 114 SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, 115 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 116 0, 12, BOOKE_PAGESZ_4K, 1), 117 118 /* 119 * *I*G - SRIO 120 * entry 14 and 15 has been used hard coded, they will be disabled 121 * in cpu_init_f, so we use entry 16 for SRIO2. 122 */ 123 #ifndef CONFIG_SPL_BUILD 124 #ifdef CONFIG_SYS_SRIO1_MEM_PHYS 125 /* *I*G* - SRIO1 */ 126 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS, 127 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 128 0, 13, BOOKE_PAGESZ_256M, 1), 129 #endif 130 #ifdef CONFIG_SYS_SRIO2_MEM_PHYS 131 /* *I*G* - SRIO2 */ 132 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS, 133 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 134 0, 16, BOOKE_PAGESZ_256M, 1), 135 #endif 136 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 137 /* 138 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for 139 * fetching ucode and ENV from master 140 */ 141 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, 142 CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, 143 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 144 0, 17, BOOKE_PAGESZ_1M, 1), 145 #endif 146 #endif 147 148 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) 149 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 150 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 151 0, 17, BOOKE_PAGESZ_2G, 1) 152 #endif 153 }; 154 155 int num_tlb_entries = ARRAY_SIZE(tlb_table); 156