1*b5b06fb7SYork Sun /* 2*b5b06fb7SYork Sun * Copyright 2011-2012 Freescale Semiconductor, Inc. 3*b5b06fb7SYork Sun * 4*b5b06fb7SYork Sun * See file CREDITS for list of people who contributed to this 5*b5b06fb7SYork Sun * project. 6*b5b06fb7SYork Sun * 7*b5b06fb7SYork Sun * This program is free software; you can redistribute it and/or 8*b5b06fb7SYork Sun * modify it under the terms of the GNU General Public License as 9*b5b06fb7SYork Sun * published by the Free Software Foundation; either version 2 of 10*b5b06fb7SYork Sun * the License, or (at your option) any later version. 11*b5b06fb7SYork Sun * 12*b5b06fb7SYork Sun * This program is distributed in the hope that it will be useful, 13*b5b06fb7SYork Sun * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*b5b06fb7SYork Sun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*b5b06fb7SYork Sun * GNU General Public License for more details. 16*b5b06fb7SYork Sun * 17*b5b06fb7SYork Sun * You should have received a copy of the GNU General Public License 18*b5b06fb7SYork Sun * along with this program; if not, write to the Free Software 19*b5b06fb7SYork Sun * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20*b5b06fb7SYork Sun * MA 02111-1307 USA 21*b5b06fb7SYork Sun */ 22*b5b06fb7SYork Sun 23*b5b06fb7SYork Sun #include <common.h> 24*b5b06fb7SYork Sun #include <asm/mmu.h> 25*b5b06fb7SYork Sun 26*b5b06fb7SYork Sun struct fsl_e_tlb_entry tlb_table[] = { 27*b5b06fb7SYork Sun /* TLB 0 - for temp stack in cache */ 28*b5b06fb7SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 29*b5b06fb7SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS, 30*b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 31*b5b06fb7SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 32*b5b06fb7SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 33*b5b06fb7SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 34*b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 35*b5b06fb7SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 36*b5b06fb7SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 37*b5b06fb7SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 38*b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 39*b5b06fb7SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 40*b5b06fb7SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 41*b5b06fb7SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 42*b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 43*b5b06fb7SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 44*b5b06fb7SYork Sun 45*b5b06fb7SYork Sun /* TLB 1 */ 46*b5b06fb7SYork Sun /* *I*** - Covers boot page */ 47*b5b06fb7SYork Sun #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 48*b5b06fb7SYork Sun /* 49*b5b06fb7SYork Sun * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 50*b5b06fb7SYork Sun * SRAM is at 0xfff00000, it covered the 0xfffff000. 51*b5b06fb7SYork Sun */ 52*b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 53*b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 54*b5b06fb7SYork Sun 0, 0, BOOKE_PAGESZ_1M, 1), 55*b5b06fb7SYork Sun #else 56*b5b06fb7SYork Sun SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 57*b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 58*b5b06fb7SYork Sun 0, 0, BOOKE_PAGESZ_4K, 1), 59*b5b06fb7SYork Sun #endif 60*b5b06fb7SYork Sun 61*b5b06fb7SYork Sun /* *I*G* - CCSRBAR */ 62*b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 63*b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 64*b5b06fb7SYork Sun 0, 1, BOOKE_PAGESZ_16M, 1), 65*b5b06fb7SYork Sun 66*b5b06fb7SYork Sun /* *I*G* - Flash, localbus */ 67*b5b06fb7SYork Sun /* This will be changed to *I*G* after relocation to RAM. */ 68*b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 69*b5b06fb7SYork Sun MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 70*b5b06fb7SYork Sun 0, 2, BOOKE_PAGESZ_256M, 1), 71*b5b06fb7SYork Sun 72*b5b06fb7SYork Sun /* *I*G* - PCI */ 73*b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 74*b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 75*b5b06fb7SYork Sun 0, 3, BOOKE_PAGESZ_256M, 1), 76*b5b06fb7SYork Sun 77*b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000, 78*b5b06fb7SYork Sun CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000, 79*b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 80*b5b06fb7SYork Sun 0, 4, BOOKE_PAGESZ_256M, 1), 81*b5b06fb7SYork Sun 82*b5b06fb7SYork Sun /* *I*G* - PCI I/O */ 83*b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 84*b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 85*b5b06fb7SYork Sun 0, 5, BOOKE_PAGESZ_64K, 1), 86*b5b06fb7SYork Sun 87*b5b06fb7SYork Sun /* Bman/Qman */ 88*b5b06fb7SYork Sun #ifdef CONFIG_SYS_BMAN_MEM_PHYS 89*b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 90*b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 91*b5b06fb7SYork Sun 0, 6, BOOKE_PAGESZ_16M, 1), 92*b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 93*b5b06fb7SYork Sun CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 94*b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 95*b5b06fb7SYork Sun 0, 7, BOOKE_PAGESZ_16M, 1), 96*b5b06fb7SYork Sun #endif 97*b5b06fb7SYork Sun #ifdef CONFIG_SYS_QMAN_MEM_PHYS 98*b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 99*b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 100*b5b06fb7SYork Sun 0, 8, BOOKE_PAGESZ_16M, 1), 101*b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 102*b5b06fb7SYork Sun CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 103*b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 104*b5b06fb7SYork Sun 0, 9, BOOKE_PAGESZ_16M, 1), 105*b5b06fb7SYork Sun #endif 106*b5b06fb7SYork Sun #ifdef CONFIG_SYS_DCSRBAR_PHYS 107*b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 108*b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 109*b5b06fb7SYork Sun 0, 10, BOOKE_PAGESZ_4M, 1), 110*b5b06fb7SYork Sun #endif 111*b5b06fb7SYork Sun #ifdef CONFIG_SYS_NAND_BASE 112*b5b06fb7SYork Sun /* 113*b5b06fb7SYork Sun * *I*G - NAND 114*b5b06fb7SYork Sun * entry 14 and 15 has been used hard coded, they will be disabled 115*b5b06fb7SYork Sun * in cpu_init_f, so we use entry 16 for nand. 116*b5b06fb7SYork Sun */ 117*b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 118*b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 119*b5b06fb7SYork Sun 0, 11, BOOKE_PAGESZ_64K, 1), 120*b5b06fb7SYork Sun #endif 121*b5b06fb7SYork Sun SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, 122*b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 123*b5b06fb7SYork Sun 0, 12, BOOKE_PAGESZ_4K, 1), 124*b5b06fb7SYork Sun 125*b5b06fb7SYork Sun }; 126*b5b06fb7SYork Sun 127*b5b06fb7SYork Sun int num_tlb_entries = ARRAY_SIZE(tlb_table); 128