1b5b06fb7SYork Sun /* 2b5b06fb7SYork Sun * Copyright 2011-2012 Freescale Semiconductor, Inc. 3b5b06fb7SYork Sun * 4b5b06fb7SYork Sun * See file CREDITS for list of people who contributed to this 5b5b06fb7SYork Sun * project. 6b5b06fb7SYork Sun * 7b5b06fb7SYork Sun * This program is free software; you can redistribute it and/or 8b5b06fb7SYork Sun * modify it under the terms of the GNU General Public License as 9b5b06fb7SYork Sun * published by the Free Software Foundation; either version 2 of 10b5b06fb7SYork Sun * the License, or (at your option) any later version. 11b5b06fb7SYork Sun * 12b5b06fb7SYork Sun * This program is distributed in the hope that it will be useful, 13b5b06fb7SYork Sun * but WITHOUT ANY WARRANTY; without even the implied warranty of 14b5b06fb7SYork Sun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15b5b06fb7SYork Sun * GNU General Public License for more details. 16b5b06fb7SYork Sun * 17b5b06fb7SYork Sun * You should have received a copy of the GNU General Public License 18b5b06fb7SYork Sun * along with this program; if not, write to the Free Software 19b5b06fb7SYork Sun * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20b5b06fb7SYork Sun * MA 02111-1307 USA 21b5b06fb7SYork Sun */ 22b5b06fb7SYork Sun 23b5b06fb7SYork Sun #include <common.h> 24b5b06fb7SYork Sun #include <asm/mmu.h> 25b5b06fb7SYork Sun 26b5b06fb7SYork Sun struct fsl_e_tlb_entry tlb_table[] = { 27b5b06fb7SYork Sun /* TLB 0 - for temp stack in cache */ 28b5b06fb7SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 29b5b06fb7SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS, 30b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 31b5b06fb7SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 32b5b06fb7SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 33b5b06fb7SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 34b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 35b5b06fb7SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 36b5b06fb7SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 37b5b06fb7SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 38b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 39b5b06fb7SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 40b5b06fb7SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 41b5b06fb7SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 42b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 43b5b06fb7SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 44b5b06fb7SYork Sun 45b5b06fb7SYork Sun /* TLB 1 */ 46b5b06fb7SYork Sun /* *I*** - Covers boot page */ 47b5b06fb7SYork Sun #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 48b5b06fb7SYork Sun /* 49b5b06fb7SYork Sun * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 50b5b06fb7SYork Sun * SRAM is at 0xfff00000, it covered the 0xfffff000. 51b5b06fb7SYork Sun */ 52b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 53b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 54b5b06fb7SYork Sun 0, 0, BOOKE_PAGESZ_1M, 1), 55b5b06fb7SYork Sun #else 56b5b06fb7SYork Sun SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 57b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 58b5b06fb7SYork Sun 0, 0, BOOKE_PAGESZ_4K, 1), 59b5b06fb7SYork Sun #endif 60b5b06fb7SYork Sun 61b5b06fb7SYork Sun /* *I*G* - CCSRBAR */ 62b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 63b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 64b5b06fb7SYork Sun 0, 1, BOOKE_PAGESZ_16M, 1), 65b5b06fb7SYork Sun 66b5b06fb7SYork Sun /* *I*G* - Flash, localbus */ 67b5b06fb7SYork Sun /* This will be changed to *I*G* after relocation to RAM. */ 68b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 69b5b06fb7SYork Sun MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 70b5b06fb7SYork Sun 0, 2, BOOKE_PAGESZ_256M, 1), 71b5b06fb7SYork Sun 72b5b06fb7SYork Sun /* *I*G* - PCI */ 73b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 74b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 75b5b06fb7SYork Sun 0, 3, BOOKE_PAGESZ_256M, 1), 76b5b06fb7SYork Sun 77b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000, 78b5b06fb7SYork Sun CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000, 79b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 80b5b06fb7SYork Sun 0, 4, BOOKE_PAGESZ_256M, 1), 81b5b06fb7SYork Sun 82b5b06fb7SYork Sun /* *I*G* - PCI I/O */ 83b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 84b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 85b5b06fb7SYork Sun 0, 5, BOOKE_PAGESZ_64K, 1), 86b5b06fb7SYork Sun 87b5b06fb7SYork Sun /* Bman/Qman */ 88b5b06fb7SYork Sun #ifdef CONFIG_SYS_BMAN_MEM_PHYS 89b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 90b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 91b5b06fb7SYork Sun 0, 6, BOOKE_PAGESZ_16M, 1), 92b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 93b5b06fb7SYork Sun CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 94b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 95b5b06fb7SYork Sun 0, 7, BOOKE_PAGESZ_16M, 1), 96b5b06fb7SYork Sun #endif 97b5b06fb7SYork Sun #ifdef CONFIG_SYS_QMAN_MEM_PHYS 98b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 99b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 100b5b06fb7SYork Sun 0, 8, BOOKE_PAGESZ_16M, 1), 101b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 102b5b06fb7SYork Sun CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 103b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 104b5b06fb7SYork Sun 0, 9, BOOKE_PAGESZ_16M, 1), 105b5b06fb7SYork Sun #endif 106b5b06fb7SYork Sun #ifdef CONFIG_SYS_DCSRBAR_PHYS 107b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 108b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 109b5b06fb7SYork Sun 0, 10, BOOKE_PAGESZ_4M, 1), 110b5b06fb7SYork Sun #endif 111b5b06fb7SYork Sun #ifdef CONFIG_SYS_NAND_BASE 112b5b06fb7SYork Sun /* 113b5b06fb7SYork Sun * *I*G - NAND 114b5b06fb7SYork Sun */ 115b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 116b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 117b5b06fb7SYork Sun 0, 11, BOOKE_PAGESZ_64K, 1), 118b5b06fb7SYork Sun #endif 119b5b06fb7SYork Sun SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, 120b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 121b5b06fb7SYork Sun 0, 12, BOOKE_PAGESZ_4K, 1), 122b5b06fb7SYork Sun 123*57966101SLiu Gang /* 124*57966101SLiu Gang * *I*G - SRIO 125*57966101SLiu Gang * entry 14 and 15 has been used hard coded, they will be disabled 126*57966101SLiu Gang * in cpu_init_f, so we use entry 16 for SRIO2. 127*57966101SLiu Gang */ 128*57966101SLiu Gang #ifdef CONFIG_SYS_SRIO1_MEM_PHYS 129*57966101SLiu Gang /* *I*G* - SRIO1 */ 130*57966101SLiu Gang SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS, 131*57966101SLiu Gang MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 132*57966101SLiu Gang 0, 13, BOOKE_PAGESZ_256M, 1), 133*57966101SLiu Gang #endif 134*57966101SLiu Gang #ifdef CONFIG_SYS_SRIO2_MEM_PHYS 135*57966101SLiu Gang /* *I*G* - SRIO2 */ 136*57966101SLiu Gang SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS, 137*57966101SLiu Gang MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 138*57966101SLiu Gang 0, 16, BOOKE_PAGESZ_256M, 1), 139*57966101SLiu Gang #endif 140b5b06fb7SYork Sun }; 141b5b06fb7SYork Sun 142b5b06fb7SYork Sun int num_tlb_entries = ARRAY_SIZE(tlb_table); 143