1b5b06fb7SYork Sun /* 2b5b06fb7SYork Sun * Copyright 2011-2012 Freescale Semiconductor, Inc. 3b5b06fb7SYork Sun * 4*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 5b5b06fb7SYork Sun */ 6b5b06fb7SYork Sun 7b5b06fb7SYork Sun #include <common.h> 8b5b06fb7SYork Sun #include <asm/mmu.h> 9b5b06fb7SYork Sun 10b5b06fb7SYork Sun struct fsl_e_tlb_entry tlb_table[] = { 11b5b06fb7SYork Sun /* TLB 0 - for temp stack in cache */ 12b5b06fb7SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 13b5b06fb7SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS, 14b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 15b5b06fb7SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 16b5b06fb7SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 17b5b06fb7SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 18b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 19b5b06fb7SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 20b5b06fb7SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 21b5b06fb7SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 22b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 23b5b06fb7SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 24b5b06fb7SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25b5b06fb7SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 26b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 27b5b06fb7SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 28b5b06fb7SYork Sun 29b5b06fb7SYork Sun /* TLB 1 */ 30b5b06fb7SYork Sun /* *I*** - Covers boot page */ 31b5b06fb7SYork Sun #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 32b5b06fb7SYork Sun /* 33b5b06fb7SYork Sun * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 34b5b06fb7SYork Sun * SRAM is at 0xfff00000, it covered the 0xfffff000. 35b5b06fb7SYork Sun */ 36b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 37b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 38b5b06fb7SYork Sun 0, 0, BOOKE_PAGESZ_1M, 1), 395870fe44SLiu Gang #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 405870fe44SLiu Gang /* 415870fe44SLiu Gang * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the 425870fe44SLiu Gang * space is at 0xfff00000, it covered the 0xfffff000. 435870fe44SLiu Gang */ 445870fe44SLiu Gang SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, 455870fe44SLiu Gang CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, 465870fe44SLiu Gang MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 475870fe44SLiu Gang 0, 0, BOOKE_PAGESZ_1M, 1), 48b5b06fb7SYork Sun #else 49b5b06fb7SYork Sun SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 50b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 51b5b06fb7SYork Sun 0, 0, BOOKE_PAGESZ_4K, 1), 52b5b06fb7SYork Sun #endif 53b5b06fb7SYork Sun 54b5b06fb7SYork Sun /* *I*G* - CCSRBAR */ 55b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 56b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57b5b06fb7SYork Sun 0, 1, BOOKE_PAGESZ_16M, 1), 58b5b06fb7SYork Sun 59b5b06fb7SYork Sun /* *I*G* - Flash, localbus */ 60b5b06fb7SYork Sun /* This will be changed to *I*G* after relocation to RAM. */ 61b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 62b5b06fb7SYork Sun MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 63b5b06fb7SYork Sun 0, 2, BOOKE_PAGESZ_256M, 1), 64b5b06fb7SYork Sun 65b5b06fb7SYork Sun /* *I*G* - PCI */ 66b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 67b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 68b5b06fb7SYork Sun 0, 3, BOOKE_PAGESZ_256M, 1), 69b5b06fb7SYork Sun 70b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000, 71b5b06fb7SYork Sun CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000, 72b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 73b5b06fb7SYork Sun 0, 4, BOOKE_PAGESZ_256M, 1), 74b5b06fb7SYork Sun 75b5b06fb7SYork Sun /* *I*G* - PCI I/O */ 76b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 77b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 78b5b06fb7SYork Sun 0, 5, BOOKE_PAGESZ_64K, 1), 79b5b06fb7SYork Sun 80b5b06fb7SYork Sun /* Bman/Qman */ 81b5b06fb7SYork Sun #ifdef CONFIG_SYS_BMAN_MEM_PHYS 82b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 83b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 84b5b06fb7SYork Sun 0, 6, BOOKE_PAGESZ_16M, 1), 85b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 86b5b06fb7SYork Sun CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 87b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 88b5b06fb7SYork Sun 0, 7, BOOKE_PAGESZ_16M, 1), 89b5b06fb7SYork Sun #endif 90b5b06fb7SYork Sun #ifdef CONFIG_SYS_QMAN_MEM_PHYS 91b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 92b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 93b5b06fb7SYork Sun 0, 8, BOOKE_PAGESZ_16M, 1), 94b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 95b5b06fb7SYork Sun CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 96b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 97b5b06fb7SYork Sun 0, 9, BOOKE_PAGESZ_16M, 1), 98b5b06fb7SYork Sun #endif 99b5b06fb7SYork Sun #ifdef CONFIG_SYS_DCSRBAR_PHYS 100b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 101b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 10249e946cbSStephen George 0, 10, BOOKE_PAGESZ_32M, 1), 103b5b06fb7SYork Sun #endif 104b5b06fb7SYork Sun #ifdef CONFIG_SYS_NAND_BASE 105b5b06fb7SYork Sun /* 106b5b06fb7SYork Sun * *I*G - NAND 107b5b06fb7SYork Sun */ 108b5b06fb7SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 109b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 110b5b06fb7SYork Sun 0, 11, BOOKE_PAGESZ_64K, 1), 111b5b06fb7SYork Sun #endif 112b5b06fb7SYork Sun SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, 113b5b06fb7SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 114b5b06fb7SYork Sun 0, 12, BOOKE_PAGESZ_4K, 1), 115b5b06fb7SYork Sun 11657966101SLiu Gang /* 11757966101SLiu Gang * *I*G - SRIO 11857966101SLiu Gang * entry 14 and 15 has been used hard coded, they will be disabled 11957966101SLiu Gang * in cpu_init_f, so we use entry 16 for SRIO2. 12057966101SLiu Gang */ 12157966101SLiu Gang #ifdef CONFIG_SYS_SRIO1_MEM_PHYS 12257966101SLiu Gang /* *I*G* - SRIO1 */ 12357966101SLiu Gang SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS, 12457966101SLiu Gang MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 12557966101SLiu Gang 0, 13, BOOKE_PAGESZ_256M, 1), 12657966101SLiu Gang #endif 12757966101SLiu Gang #ifdef CONFIG_SYS_SRIO2_MEM_PHYS 12857966101SLiu Gang /* *I*G* - SRIO2 */ 12957966101SLiu Gang SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS, 13057966101SLiu Gang MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 13157966101SLiu Gang 0, 16, BOOKE_PAGESZ_256M, 1), 13257966101SLiu Gang #endif 1335870fe44SLiu Gang #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 1345870fe44SLiu Gang /* 1355870fe44SLiu Gang * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for 1365870fe44SLiu Gang * fetching ucode and ENV from master 1375870fe44SLiu Gang */ 1385870fe44SLiu Gang SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, 1395870fe44SLiu Gang CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, 1405870fe44SLiu Gang MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 1415870fe44SLiu Gang 0, 17, BOOKE_PAGESZ_1M, 1), 1425870fe44SLiu Gang #endif 143b5b06fb7SYork Sun }; 144b5b06fb7SYork Sun 145b5b06fb7SYork Sun int num_tlb_entries = ARRAY_SIZE(tlb_table); 146