1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2b5b06fb7SYork Sun /* 3b5b06fb7SYork Sun * Copyright 2012 Freescale Semiconductor, Inc. 4b5b06fb7SYork Sun */ 5b5b06fb7SYork Sun 6b5b06fb7SYork Sun #ifndef __B4860QDS_QIXIS_H__ 7b5b06fb7SYork Sun #define __B4860QDS_QIXIS_H__ 8b5b06fb7SYork Sun 9b5b06fb7SYork Sun /* Definitions of QIXIS Registers for B4860QDS */ 10b5b06fb7SYork Sun 11b5b06fb7SYork Sun /* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ 12b5b06fb7SYork Sun #define BRDCFG4_EMISEL_MASK 0xE0 13b5b06fb7SYork Sun #define BRDCFG4_EMISEL_SHIFT 5 14b5b06fb7SYork Sun 15b5b06fb7SYork Sun /* CLK */ 16b5b06fb7SYork Sun #define QIXIS_CLK_66 0x0 17b5b06fb7SYork Sun #define QIXIS_CLK_100 0x1 18b5b06fb7SYork Sun #define QIXIS_CLK_125 0x2 19b5b06fb7SYork Sun #define QIXIS_CLK_133 0x3 20b5b06fb7SYork Sun 21b5b06fb7SYork Sun #define QIXIS_SRDS1CLK_122 0x5a 22b5b06fb7SYork Sun #define QIXIS_SRDS1CLK_125 0x5e 23ffee1ddeSZhao Qiang 24ffee1ddeSZhao Qiang /* SGMII */ 25ffee1ddeSZhao Qiang #define PHY_BASE_ADDR 0x18 26ffee1ddeSZhao Qiang #define PORT_NUM 0x04 27ffee1ddeSZhao Qiang #define REGNUM 0x00 28b5b06fb7SYork Sun #endif 29