1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <command.h> 8 #include <i2c.h> 9 #include <netdev.h> 10 #include <linux/compiler.h> 11 #include <asm/mmu.h> 12 #include <asm/processor.h> 13 #include <linux/errno.h> 14 #include <asm/cache.h> 15 #include <asm/immap_85xx.h> 16 #include <asm/fsl_law.h> 17 #include <asm/fsl_serdes.h> 18 #include <asm/fsl_liodn.h> 19 #include <fm_eth.h> 20 #include <hwconfig.h> 21 22 #include "../common/qixis.h" 23 #include "../common/vsc3316_3308.h" 24 #include "../common/idt8t49n222a_serdes_clk.h" 25 #include "../common/zm7300.h" 26 #include "b4860qds.h" 27 #include "b4860qds_qixis.h" 28 #include "b4860qds_crossbar_con.h" 29 30 #define CLK_MUX_SEL_MASK 0x4 31 #define ETH_PHY_CLK_OUT 0x4 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 int checkboard(void) 36 { 37 char buf[64]; 38 u8 sw; 39 struct cpu_type *cpu = gd->arch.cpu; 40 static const char *const freq[] = {"100", "125", "156.25", "161.13", 41 "122.88", "122.88", "122.88"}; 42 int clock; 43 44 printf("Board: %sQDS, ", cpu->name); 45 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", 46 QIXIS_READ(id), QIXIS_READ(arch)); 47 48 sw = QIXIS_READ(brdcfg[0]); 49 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 50 51 if (sw < 0x8) 52 printf("vBank: %d\n", sw); 53 else if (sw >= 0x8 && sw <= 0xE) 54 puts("NAND\n"); 55 else 56 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 57 58 printf("FPGA: v%d (%s), build %d", 59 (int)QIXIS_READ(scver), qixis_read_tag(buf), 60 (int)qixis_read_minor()); 61 /* the timestamp string contains "\n" at the end */ 62 printf(" on %s", qixis_read_time(buf)); 63 64 /* 65 * Display the actual SERDES reference clocks as configured by the 66 * dip switches on the board. Note that the SWx registers could 67 * technically be set to force the reference clocks to match the 68 * values that the SERDES expects (or vice versa). For now, however, 69 * we just display both values and hope the user notices when they 70 * don't match. 71 */ 72 puts("SERDES Reference Clocks: "); 73 sw = QIXIS_READ(brdcfg[2]); 74 clock = (sw >> 5) & 7; 75 printf("Bank1=%sMHz ", freq[clock]); 76 sw = QIXIS_READ(brdcfg[4]); 77 clock = (sw >> 6) & 3; 78 printf("Bank2=%sMHz\n", freq[clock]); 79 80 return 0; 81 } 82 83 int select_i2c_ch_pca(u8 ch) 84 { 85 int ret; 86 87 /* Selecting proper channel via PCA*/ 88 ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1); 89 if (ret) { 90 printf("PCA: failed to select proper channel.\n"); 91 return ret; 92 } 93 94 return 0; 95 } 96 97 /* 98 * read_voltage from sensor on I2C bus 99 * We use average of 4 readings, waiting for 532us befor another reading 100 */ 101 #define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */ 102 #define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */ 103 104 static inline int read_voltage(void) 105 { 106 int i, ret, voltage_read = 0; 107 u16 vol_mon; 108 109 for (i = 0; i < NUM_READINGS; i++) { 110 ret = i2c_read(I2C_VOL_MONITOR_ADDR, 111 I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2); 112 if (ret) { 113 printf("VID: failed to read core voltage\n"); 114 return ret; 115 } 116 if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { 117 printf("VID: Core voltage sensor error\n"); 118 return -1; 119 } 120 debug("VID: bus voltage reads 0x%04x\n", vol_mon); 121 /* LSB = 4mv */ 122 voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; 123 udelay(WAIT_FOR_ADC); 124 } 125 /* calculate the average */ 126 voltage_read /= NUM_READINGS; 127 128 return voltage_read; 129 } 130 131 static int adjust_vdd(ulong vdd_override) 132 { 133 int re_enable = disable_interrupts(); 134 ccsr_gur_t __iomem *gur = 135 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 136 u32 fusesr; 137 u8 vid; 138 int vdd_target, vdd_last; 139 int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */ 140 int ret; 141 unsigned int orig_i2c_speed; 142 unsigned long vdd_string_override; 143 char *vdd_string; 144 static const uint16_t vdd[32] = { 145 0, /* unused */ 146 9875, /* 0.9875V */ 147 9750, 148 9625, 149 9500, 150 9375, 151 9250, 152 9125, 153 9000, 154 8875, 155 8750, 156 8625, 157 8500, 158 8375, 159 8250, 160 8125, 161 10000, /* 1.0000V */ 162 10125, 163 10250, 164 10375, 165 10500, 166 10625, 167 10750, 168 10875, 169 11000, 170 0, /* reserved */ 171 }; 172 struct vdd_drive { 173 u8 vid; 174 unsigned voltage; 175 }; 176 177 ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR); 178 if (ret) { 179 printf("VID: I2c failed to switch channel\n"); 180 ret = -1; 181 goto exit; 182 } 183 184 /* get the voltage ID from fuse status register */ 185 fusesr = in_be32(&gur->dcfg_fusesr); 186 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & 187 FSL_CORENET_DCFG_FUSESR_VID_MASK; 188 if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) { 189 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & 190 FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; 191 } 192 vdd_target = vdd[vid]; 193 debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n", 194 vid, vdd_target/10); 195 196 /* check override variable for overriding VDD */ 197 vdd_string = env_get("b4qds_vdd_mv"); 198 if (vdd_override == 0 && vdd_string && 199 !strict_strtoul(vdd_string, 10, &vdd_string_override)) 200 vdd_override = vdd_string_override; 201 if (vdd_override >= 819 && vdd_override <= 1212) { 202 vdd_target = vdd_override * 10; /* convert to 1/10 mV */ 203 debug("VDD override is %lu\n", vdd_override); 204 } else if (vdd_override != 0) { 205 printf("Invalid value.\n"); 206 } 207 208 if (vdd_target == 0) { 209 printf("VID: VID not used\n"); 210 ret = 0; 211 goto exit; 212 } 213 214 /* 215 * Read voltage monitor to check real voltage. 216 * Voltage monitor LSB is 4mv. 217 */ 218 vdd_last = read_voltage(); 219 if (vdd_last < 0) { 220 printf("VID: abort VID adjustment\n"); 221 ret = -1; 222 goto exit; 223 } 224 225 debug("VID: Core voltage is at %d mV\n", vdd_last); 226 ret = select_i2c_ch_pca(I2C_MUX_CH_DPM); 227 if (ret) { 228 printf("VID: I2c failed to switch channel to DPM\n"); 229 ret = -1; 230 goto exit; 231 } 232 233 /* Round up to the value of step of Voltage regulator */ 234 voltage = roundup(vdd_target, ZM_STEP); 235 debug("VID: rounded up voltage = %d\n", voltage); 236 237 /* lower the speed to 100kHz to access ZM7300 device */ 238 debug("VID: Setting bus speed to 100KHz if not already set\n"); 239 orig_i2c_speed = i2c_get_bus_speed(); 240 if (orig_i2c_speed != 100000) 241 i2c_set_bus_speed(100000); 242 243 /* Read the existing level on board, if equal to requsted one, 244 no need to re-set */ 245 existing_voltage = zm_read_voltage(); 246 247 /* allowing the voltage difference of one step 0.0125V acceptable */ 248 if ((existing_voltage >= voltage) && 249 (existing_voltage < (voltage + ZM_STEP))) { 250 debug("VID: voltage already set as requested,returning\n"); 251 ret = existing_voltage; 252 goto out; 253 } 254 debug("VID: Changing voltage for board from %dmV to %dmV\n", 255 existing_voltage/10, voltage/10); 256 257 if (zm_disable_wp() < 0) { 258 ret = -1; 259 goto out; 260 } 261 /* Change Voltage: the change is done through all the steps in the 262 way, to avoid reset to the board due to power good signal fail 263 in big voltage change gap jump. 264 */ 265 if (existing_voltage > voltage) { 266 temp_voltage = existing_voltage - ZM_STEP; 267 while (temp_voltage >= voltage) { 268 ret = zm_write_voltage(temp_voltage); 269 if (ret == temp_voltage) { 270 temp_voltage -= ZM_STEP; 271 } else { 272 /* ZM7300 device failed to set 273 * the voltage */ 274 printf 275 ("VID:Stepping down vol failed:%dmV\n", 276 temp_voltage/10); 277 ret = -1; 278 goto out; 279 } 280 } 281 } else { 282 temp_voltage = existing_voltage + ZM_STEP; 283 while (temp_voltage < (voltage + ZM_STEP)) { 284 ret = zm_write_voltage(temp_voltage); 285 if (ret == temp_voltage) { 286 temp_voltage += ZM_STEP; 287 } else { 288 /* ZM7300 device failed to set 289 * the voltage */ 290 printf 291 ("VID:Stepping up vol failed:%dmV\n", 292 temp_voltage/10); 293 ret = -1; 294 goto out; 295 } 296 } 297 } 298 299 if (zm_enable_wp() < 0) 300 ret = -1; 301 302 /* restore the speed to 400kHz */ 303 out: debug("VID: Restore the I2C bus speed to %dKHz\n", 304 orig_i2c_speed/1000); 305 i2c_set_bus_speed(orig_i2c_speed); 306 if (ret < 0) 307 goto exit; 308 309 ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR); 310 if (ret) { 311 printf("VID: I2c failed to switch channel\n"); 312 ret = -1; 313 goto exit; 314 } 315 vdd_last = read_voltage(); 316 select_i2c_ch_pca(I2C_CH_DEFAULT); 317 318 if (vdd_last > 0) 319 printf("VID: Core voltage %d mV\n", vdd_last); 320 else 321 ret = -1; 322 323 exit: 324 if (re_enable) 325 enable_interrupts(); 326 return ret; 327 } 328 329 int configure_vsc3316_3308(void) 330 { 331 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 332 unsigned int num_vsc16_con, num_vsc08_con; 333 u32 serdes1_prtcl, serdes2_prtcl; 334 int ret; 335 char buffer[HWCONFIG_BUFFER_SIZE]; 336 char *buf = NULL; 337 338 serdes1_prtcl = in_be32(&gur->rcwsr[4]) & 339 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 340 if (!serdes1_prtcl) { 341 printf("SERDES1 is not enabled\n"); 342 return 0; 343 } 344 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 345 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); 346 347 serdes2_prtcl = in_be32(&gur->rcwsr[4]) & 348 FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 349 if (!serdes2_prtcl) { 350 printf("SERDES2 is not enabled\n"); 351 return 0; 352 } 353 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 354 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); 355 356 switch (serdes1_prtcl) { 357 case 0x29: 358 case 0x2a: 359 case 0x2C: 360 case 0x2D: 361 case 0x2E: 362 /* 363 * Configuration: 364 * SERDES: 1 365 * Lanes: A,B: SGMII 366 * Lanes: C,D,E,F,G,H: CPRI 367 */ 368 debug("Configuring crossbar to use onboard SGMII PHYs:" 369 "srds_prctl:%x\n", serdes1_prtcl); 370 num_vsc16_con = NUM_CON_VSC3316; 371 /* Configure VSC3316 crossbar switch */ 372 ret = select_i2c_ch_pca(I2C_CH_VSC3316); 373 if (!ret) { 374 ret = vsc3316_config(VSC3316_TX_ADDRESS, 375 vsc16_tx_4sfp_sgmii_12_56, 376 num_vsc16_con); 377 if (ret) 378 return ret; 379 ret = vsc3316_config(VSC3316_RX_ADDRESS, 380 vsc16_rx_4sfp_sgmii_12_56, 381 num_vsc16_con); 382 if (ret) 383 return ret; 384 } else { 385 return ret; 386 } 387 break; 388 389 case 0x01: 390 case 0x02: 391 case 0x04: 392 case 0x05: 393 case 0x06: 394 case 0x07: 395 case 0x08: 396 case 0x09: 397 case 0x0A: 398 case 0x0B: 399 case 0x0C: 400 case 0x2F: 401 case 0x30: 402 case 0x32: 403 case 0x33: 404 case 0x34: 405 case 0x39: 406 case 0x3A: 407 case 0x3C: 408 case 0x3D: 409 case 0x5C: 410 case 0x5D: 411 /* 412 * Configuration: 413 * SERDES: 1 414 * Lanes: A,B: AURORA 415 * Lanes: C,d: SGMII 416 * Lanes: E,F,G,H: CPRI 417 */ 418 debug("Configuring crossbar for Aurora, SGMII 3 and 4," 419 " and CPRI. srds_prctl:%x\n", serdes1_prtcl); 420 num_vsc16_con = NUM_CON_VSC3316; 421 /* Configure VSC3316 crossbar switch */ 422 ret = select_i2c_ch_pca(I2C_CH_VSC3316); 423 if (!ret) { 424 ret = vsc3316_config(VSC3316_TX_ADDRESS, 425 vsc16_tx_sfp_sgmii_aurora, 426 num_vsc16_con); 427 if (ret) 428 return ret; 429 ret = vsc3316_config(VSC3316_RX_ADDRESS, 430 vsc16_rx_sfp_sgmii_aurora, 431 num_vsc16_con); 432 if (ret) 433 return ret; 434 } else { 435 return ret; 436 } 437 break; 438 439 #ifdef CONFIG_ARCH_B4420 440 case 0x17: 441 case 0x18: 442 /* 443 * Configuration: 444 * SERDES: 1 445 * Lanes: A,B,C,D: SGMII 446 * Lanes: E,F,G,H: CPRI 447 */ 448 debug("Configuring crossbar to use onboard SGMII PHYs:" 449 "srds_prctl:%x\n", serdes1_prtcl); 450 num_vsc16_con = NUM_CON_VSC3316; 451 /* Configure VSC3316 crossbar switch */ 452 ret = select_i2c_ch_pca(I2C_CH_VSC3316); 453 if (!ret) { 454 ret = vsc3316_config(VSC3316_TX_ADDRESS, 455 vsc16_tx_sgmii_lane_cd, num_vsc16_con); 456 if (ret) 457 return ret; 458 ret = vsc3316_config(VSC3316_RX_ADDRESS, 459 vsc16_rx_sgmii_lane_cd, num_vsc16_con); 460 if (ret) 461 return ret; 462 } else { 463 return ret; 464 } 465 break; 466 #endif 467 468 case 0x3E: 469 case 0x0D: 470 case 0x0E: 471 case 0x12: 472 num_vsc16_con = NUM_CON_VSC3316; 473 /* Configure VSC3316 crossbar switch */ 474 ret = select_i2c_ch_pca(I2C_CH_VSC3316); 475 if (!ret) { 476 ret = vsc3316_config(VSC3316_TX_ADDRESS, 477 vsc16_tx_sfp, num_vsc16_con); 478 if (ret) 479 return ret; 480 ret = vsc3316_config(VSC3316_RX_ADDRESS, 481 vsc16_rx_sfp, num_vsc16_con); 482 if (ret) 483 return ret; 484 } else { 485 return ret; 486 } 487 break; 488 default: 489 printf("WARNING:VSC crossbars programming not supported for:%x" 490 " SerDes1 Protocol.\n", serdes1_prtcl); 491 return -1; 492 } 493 494 num_vsc08_con = NUM_CON_VSC3308; 495 /* Configure VSC3308 crossbar switch */ 496 ret = select_i2c_ch_pca(I2C_CH_VSC3308); 497 switch (serdes2_prtcl) { 498 #ifdef CONFIG_ARCH_B4420 499 case 0x9d: 500 #endif 501 case 0x9E: 502 case 0x9A: 503 case 0x98: 504 case 0x48: 505 case 0x49: 506 case 0x4E: 507 case 0x79: 508 case 0x7A: 509 if (!ret) { 510 ret = vsc3308_config(VSC3308_TX_ADDRESS, 511 vsc08_tx_amc, num_vsc08_con); 512 if (ret) 513 return ret; 514 ret = vsc3308_config(VSC3308_RX_ADDRESS, 515 vsc08_rx_amc, num_vsc08_con); 516 if (ret) 517 return ret; 518 } else { 519 return ret; 520 } 521 break; 522 case 0x80: 523 case 0x81: 524 case 0x82: 525 case 0x83: 526 case 0x84: 527 case 0x85: 528 case 0x86: 529 case 0x87: 530 case 0x88: 531 case 0x89: 532 case 0x8a: 533 case 0x8b: 534 case 0x8c: 535 case 0x8d: 536 case 0x8e: 537 case 0xb1: 538 case 0xb2: 539 if (!ret) { 540 /* 541 * Extract hwconfig from environment since environment 542 * is not setup properly yet 543 */ 544 env_get_f("hwconfig", buffer, sizeof(buffer)); 545 buf = buffer; 546 547 if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2", 548 "sfp_amc", "sfp", buf)) { 549 #ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR 550 /* change default VSC3308 for XFI erratum */ 551 ret = vsc3308_config_adjust(VSC3308_TX_ADDRESS, 552 vsc08_tx_sfp, num_vsc08_con); 553 if (ret) 554 return ret; 555 556 ret = vsc3308_config_adjust(VSC3308_RX_ADDRESS, 557 vsc08_rx_sfp, num_vsc08_con); 558 if (ret) 559 return ret; 560 #else 561 ret = vsc3308_config(VSC3308_TX_ADDRESS, 562 vsc08_tx_sfp, num_vsc08_con); 563 if (ret) 564 return ret; 565 566 ret = vsc3308_config(VSC3308_RX_ADDRESS, 567 vsc08_rx_sfp, num_vsc08_con); 568 if (ret) 569 return ret; 570 #endif 571 } else { 572 ret = vsc3308_config(VSC3308_TX_ADDRESS, 573 vsc08_tx_amc, num_vsc08_con); 574 if (ret) 575 return ret; 576 577 ret = vsc3308_config(VSC3308_RX_ADDRESS, 578 vsc08_rx_amc, num_vsc08_con); 579 if (ret) 580 return ret; 581 } 582 583 } else { 584 return ret; 585 } 586 break; 587 default: 588 printf("WARNING:VSC crossbars programming not supported for: %x" 589 " SerDes2 Protocol.\n", serdes2_prtcl); 590 return -1; 591 } 592 593 return 0; 594 } 595 596 static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num) 597 { 598 u32 rst_err; 599 600 /* Steps For SerDes PLLs reset and reconfiguration 601 * or PLL power-up procedure 602 */ 603 debug("CALIBRATE PLL:%d\n", pll_num); 604 clrbits_be32(&srds_regs->bank[pll_num].rstctl, 605 SRDS_RSTCTL_SDRST_B); 606 udelay(10); 607 clrbits_be32(&srds_regs->bank[pll_num].rstctl, 608 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); 609 udelay(10); 610 setbits_be32(&srds_regs->bank[pll_num].rstctl, 611 SRDS_RSTCTL_RST); 612 setbits_be32(&srds_regs->bank[pll_num].rstctl, 613 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B 614 | SRDS_RSTCTL_SDRST_B)); 615 616 udelay(20); 617 618 /* Check whether PLL has been locked or not */ 619 rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) & 620 SRDS_RSTCTL_RSTERR; 621 rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT; 622 debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err); 623 if (rst_err) 624 return rst_err; 625 626 return rst_err; 627 } 628 629 static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num) 630 { 631 int ret = 0; 632 u32 fcap, dcbias, bcap, pllcr1, pllcr0; 633 634 if (calibrate_pll(srds_regs, pll_num)) { 635 /* STEP 1 */ 636 /* Read fcap, dcbias and bcap value */ 637 clrbits_be32(&srds_regs->bank[pll_num].pllcr0, 638 SRDS_PLLCR0_DCBIAS_OUT_EN); 639 fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) & 640 SRDS_PLLSR2_FCAP; 641 fcap >>= SRDS_PLLSR2_FCAP_SHIFT; 642 bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) & 643 SRDS_PLLSR2_BCAP_EN; 644 bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT; 645 setbits_be32(&srds_regs->bank[pll_num].pllcr0, 646 SRDS_PLLCR0_DCBIAS_OUT_EN); 647 dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) & 648 SRDS_PLLSR2_DCBIAS; 649 dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT; 650 debug("values of bcap:%x, fcap:%x and dcbias:%x\n", 651 bcap, fcap, dcbias); 652 if (fcap == 0 && bcap == 1) { 653 /* Step 3 */ 654 clrbits_be32(&srds_regs->bank[pll_num].rstctl, 655 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B 656 | SRDS_RSTCTL_SDRST_B)); 657 clrbits_be32(&srds_regs->bank[pll_num].pllcr1, 658 SRDS_PLLCR1_BCAP_EN); 659 setbits_be32(&srds_regs->bank[pll_num].pllcr1, 660 SRDS_PLLCR1_BCAP_OVD); 661 if (calibrate_pll(srds_regs, pll_num)) { 662 /*save the fcap, dcbias and bcap values*/ 663 clrbits_be32(&srds_regs->bank[pll_num].pllcr0, 664 SRDS_PLLCR0_DCBIAS_OUT_EN); 665 fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) 666 & SRDS_PLLSR2_FCAP; 667 fcap >>= SRDS_PLLSR2_FCAP_SHIFT; 668 bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) 669 & SRDS_PLLSR2_BCAP_EN; 670 bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT; 671 setbits_be32(&srds_regs->bank[pll_num].pllcr0, 672 SRDS_PLLCR0_DCBIAS_OUT_EN); 673 dcbias = in_be32 674 (&srds_regs->bank[pll_num].pllsr2) & 675 SRDS_PLLSR2_DCBIAS; 676 dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT; 677 678 /* Step 4*/ 679 clrbits_be32(&srds_regs->bank[pll_num].rstctl, 680 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B 681 | SRDS_RSTCTL_SDRST_B)); 682 setbits_be32(&srds_regs->bank[pll_num].pllcr1, 683 SRDS_PLLCR1_BYP_CAL); 684 clrbits_be32(&srds_regs->bank[pll_num].pllcr1, 685 SRDS_PLLCR1_BCAP_EN); 686 setbits_be32(&srds_regs->bank[pll_num].pllcr1, 687 SRDS_PLLCR1_BCAP_OVD); 688 /* change the fcap and dcbias to the saved 689 * values from Step 3 */ 690 clrbits_be32(&srds_regs->bank[pll_num].pllcr1, 691 SRDS_PLLCR1_PLL_FCAP); 692 pllcr1 = (in_be32 693 (&srds_regs->bank[pll_num].pllcr1)| 694 (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT)); 695 out_be32(&srds_regs->bank[pll_num].pllcr1, 696 pllcr1); 697 clrbits_be32(&srds_regs->bank[pll_num].pllcr0, 698 SRDS_PLLCR0_DCBIAS_OVRD); 699 pllcr0 = (in_be32 700 (&srds_regs->bank[pll_num].pllcr0)| 701 (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT)); 702 out_be32(&srds_regs->bank[pll_num].pllcr0, 703 pllcr0); 704 ret = calibrate_pll(srds_regs, pll_num); 705 if (ret) 706 return ret; 707 } else { 708 goto out; 709 } 710 } else { /* Step 5 */ 711 clrbits_be32(&srds_regs->bank[pll_num].rstctl, 712 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B 713 | SRDS_RSTCTL_SDRST_B)); 714 udelay(10); 715 /* Change the fcap, dcbias, and bcap to the 716 * values from Step 1 */ 717 setbits_be32(&srds_regs->bank[pll_num].pllcr1, 718 SRDS_PLLCR1_BYP_CAL); 719 clrbits_be32(&srds_regs->bank[pll_num].pllcr1, 720 SRDS_PLLCR1_PLL_FCAP); 721 pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)| 722 (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT)); 723 out_be32(&srds_regs->bank[pll_num].pllcr1, 724 pllcr1); 725 clrbits_be32(&srds_regs->bank[pll_num].pllcr0, 726 SRDS_PLLCR0_DCBIAS_OVRD); 727 pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)| 728 (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT)); 729 out_be32(&srds_regs->bank[pll_num].pllcr0, 730 pllcr0); 731 clrbits_be32(&srds_regs->bank[pll_num].pllcr1, 732 SRDS_PLLCR1_BCAP_EN); 733 setbits_be32(&srds_regs->bank[pll_num].pllcr1, 734 SRDS_PLLCR1_BCAP_OVD); 735 ret = calibrate_pll(srds_regs, pll_num); 736 if (ret) 737 return ret; 738 } 739 } 740 out: 741 return 0; 742 } 743 744 static int check_serdes_pll_locks(void) 745 { 746 serdes_corenet_t *srds1_regs = 747 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 748 serdes_corenet_t *srds2_regs = 749 (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR; 750 int i, ret1, ret2; 751 752 debug("\nSerDes1 Lock check\n"); 753 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { 754 ret1 = check_pll_locks(srds1_regs, i); 755 if (ret1) { 756 printf("SerDes1, PLL:%d didnt lock\n", i); 757 return ret1; 758 } 759 } 760 debug("\nSerDes2 Lock check\n"); 761 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { 762 ret2 = check_pll_locks(srds2_regs, i); 763 if (ret2) { 764 printf("SerDes2, PLL:%d didnt lock\n", i); 765 return ret2; 766 } 767 } 768 769 return 0; 770 } 771 772 int config_serdes1_refclks(void) 773 { 774 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 775 serdes_corenet_t *srds_regs = 776 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 777 u32 serdes1_prtcl, lane; 778 unsigned int flag_sgmii_aurora_prtcl = 0; 779 int i; 780 int ret = 0; 781 782 serdes1_prtcl = in_be32(&gur->rcwsr[4]) & 783 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 784 if (!serdes1_prtcl) { 785 printf("SERDES1 is not enabled\n"); 786 return -1; 787 } 788 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 789 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); 790 791 /* To prevent generation of reset request from SerDes 792 * while changing the refclks, By setting SRDS_RST_MSK bit, 793 * SerDes reset event cannot cause a reset request 794 */ 795 setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); 796 797 /* Reconfigure IDT idt8t49n222a device for CPRI to work 798 * For this SerDes1's Refclk1 and refclk2 need to be set 799 * to 122.88MHz 800 */ 801 switch (serdes1_prtcl) { 802 case 0x29: 803 case 0x2A: 804 case 0x2C: 805 case 0x2D: 806 case 0x2E: 807 case 0x01: 808 case 0x02: 809 case 0x04: 810 case 0x05: 811 case 0x06: 812 case 0x07: 813 case 0x08: 814 case 0x09: 815 case 0x0A: 816 case 0x0B: 817 case 0x0C: 818 case 0x2F: 819 case 0x30: 820 case 0x32: 821 case 0x33: 822 case 0x34: 823 case 0x39: 824 case 0x3A: 825 case 0x3C: 826 case 0x3D: 827 case 0x5C: 828 case 0x5D: 829 debug("Configuring idt8t49n222a for CPRI SerDes clks:" 830 " for srds_prctl:%x\n", serdes1_prtcl); 831 ret = select_i2c_ch_pca(I2C_CH_IDT); 832 if (!ret) { 833 ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1, 834 SERDES_REFCLK_122_88, 835 SERDES_REFCLK_122_88, 0); 836 if (ret) { 837 printf("IDT8T49N222A configuration failed.\n"); 838 goto out; 839 } else 840 debug("IDT8T49N222A configured.\n"); 841 } else { 842 goto out; 843 } 844 select_i2c_ch_pca(I2C_CH_DEFAULT); 845 846 /* Change SerDes1's Refclk1 to 125MHz for on board 847 * SGMIIs or Aurora to work 848 */ 849 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 850 enum srds_prtcl lane_prtcl = serdes_get_prtcl 851 (0, serdes1_prtcl, lane); 852 switch (lane_prtcl) { 853 case SGMII_FM1_DTSEC1: 854 case SGMII_FM1_DTSEC2: 855 case SGMII_FM1_DTSEC3: 856 case SGMII_FM1_DTSEC4: 857 case SGMII_FM1_DTSEC5: 858 case SGMII_FM1_DTSEC6: 859 case AURORA: 860 flag_sgmii_aurora_prtcl++; 861 break; 862 default: 863 break; 864 } 865 } 866 867 if (flag_sgmii_aurora_prtcl) 868 QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); 869 870 /* Steps For SerDes PLLs reset and reconfiguration after 871 * changing SerDes's refclks 872 */ 873 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { 874 debug("For PLL%d reset and reconfiguration after" 875 " changing refclks\n", i+1); 876 clrbits_be32(&srds_regs->bank[i].rstctl, 877 SRDS_RSTCTL_SDRST_B); 878 udelay(10); 879 clrbits_be32(&srds_regs->bank[i].rstctl, 880 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); 881 udelay(10); 882 setbits_be32(&srds_regs->bank[i].rstctl, 883 SRDS_RSTCTL_RST); 884 setbits_be32(&srds_regs->bank[i].rstctl, 885 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B 886 | SRDS_RSTCTL_SDRST_B)); 887 } 888 break; 889 default: 890 printf("WARNING:IDT8T49N222A configuration not" 891 " supported for:%x SerDes1 Protocol.\n", 892 serdes1_prtcl); 893 } 894 895 out: 896 /* Clearing SRDS_RST_MSK bit as now 897 * SerDes reset event can cause a reset request 898 */ 899 clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); 900 return ret; 901 } 902 903 int config_serdes2_refclks(void) 904 { 905 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 906 serdes_corenet_t *srds2_regs = 907 (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR; 908 u32 serdes2_prtcl; 909 int ret = 0; 910 int i; 911 912 serdes2_prtcl = in_be32(&gur->rcwsr[4]) & 913 FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 914 if (!serdes2_prtcl) { 915 debug("SERDES2 is not enabled\n"); 916 return -ENODEV; 917 } 918 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 919 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); 920 921 /* To prevent generation of reset request from SerDes 922 * while changing the refclks, By setting SRDS_RST_MSK bit, 923 * SerDes reset event cannot cause a reset request 924 */ 925 setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); 926 927 /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work 928 * For this SerDes2's Refclk1 need to be set to 100MHz 929 */ 930 switch (serdes2_prtcl) { 931 #ifdef CONFIG_ARCH_B4420 932 case 0x9d: 933 #endif 934 case 0x9E: 935 case 0x9A: 936 /* fallthrough */ 937 case 0xb1: 938 case 0xb2: 939 debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n", 940 serdes2_prtcl); 941 ret = select_i2c_ch_pca(I2C_CH_IDT); 942 if (!ret) { 943 ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2, 944 SERDES_REFCLK_100, 945 SERDES_REFCLK_156_25, 0); 946 if (ret) { 947 printf("IDT8T49N222A configuration failed.\n"); 948 goto out; 949 } else 950 debug("IDT8T49N222A configured.\n"); 951 } else { 952 goto out; 953 } 954 select_i2c_ch_pca(I2C_CH_DEFAULT); 955 956 /* Steps For SerDes PLLs reset and reconfiguration after 957 * changing SerDes's refclks 958 */ 959 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { 960 clrbits_be32(&srds2_regs->bank[i].rstctl, 961 SRDS_RSTCTL_SDRST_B); 962 udelay(10); 963 clrbits_be32(&srds2_regs->bank[i].rstctl, 964 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); 965 udelay(10); 966 setbits_be32(&srds2_regs->bank[i].rstctl, 967 SRDS_RSTCTL_RST); 968 setbits_be32(&srds2_regs->bank[i].rstctl, 969 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B 970 | SRDS_RSTCTL_SDRST_B)); 971 972 udelay(10); 973 } 974 break; 975 default: 976 printf("IDT configuration not supported for:%x S2 Protocol.\n", 977 serdes2_prtcl); 978 } 979 980 out: 981 /* Clearing SRDS_RST_MSK bit as now 982 * SerDes reset event can cause a reset request 983 */ 984 clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); 985 return ret; 986 } 987 988 int board_early_init_r(void) 989 { 990 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 991 int flash_esel = find_tlb_idx((void *)flashbase, 1); 992 int ret; 993 u32 svr = SVR_SOC_VER(get_svr()); 994 995 /* Create law for MAPLE only for personalities having MAPLE */ 996 if ((svr == SVR_B4860) || (svr == SVR_B4440) || 997 (svr == SVR_B4420) || (svr == SVR_B4220)) { 998 set_next_law(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M, 999 LAW_TRGT_IF_MAPLE); 1000 } 1001 1002 /* 1003 * Remap Boot flash + PROMJET region to caching-inhibited 1004 * so that flash can be erased properly. 1005 */ 1006 1007 /* Flush d-cache and invalidate i-cache of any FLASH data */ 1008 flush_dcache(); 1009 invalidate_icache(); 1010 1011 if (flash_esel == -1) { 1012 /* very unlikely unless something is messed up */ 1013 puts("Error: Could not find TLB for FLASH BASE\n"); 1014 flash_esel = 2; /* give our best effort to continue */ 1015 } else { 1016 /* invalidate existing TLB entry for flash + promjet */ 1017 disable_tlb(flash_esel); 1018 } 1019 1020 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 1021 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 1022 0, flash_esel, BOOKE_PAGESZ_256M, 1); 1023 1024 /* 1025 * Adjust core voltage according to voltage ID 1026 * This function changes I2C mux to channel 2. 1027 */ 1028 if (adjust_vdd(0) < 0) 1029 printf("Warning: Adjusting core voltage failed\n"); 1030 1031 /* SerDes1 refclks need to be set again, as default clks 1032 * are not suitable for CPRI and onboard SGMIIs to work 1033 * simultaneously. 1034 * This function will set SerDes1's Refclk1 and refclk2 1035 * as per SerDes1 protocols 1036 */ 1037 if (config_serdes1_refclks()) 1038 printf("SerDes1 Refclks couldn't set properly.\n"); 1039 else 1040 printf("SerDes1 Refclks have been set.\n"); 1041 1042 /* SerDes2 refclks need to be set again, as default clks 1043 * are not suitable for PCIe SATA to work 1044 * This function will set SerDes2's Refclk1 and refclk2 1045 * for SerDes2 protocols having PCIe in them 1046 * for PCIe SATA to work 1047 */ 1048 ret = config_serdes2_refclks(); 1049 if (!ret) 1050 printf("SerDes2 Refclks have been set.\n"); 1051 else if (ret == -ENODEV) 1052 printf("SerDes disable, Refclks couldn't change.\n"); 1053 else 1054 printf("SerDes2 Refclk reconfiguring failed.\n"); 1055 1056 #if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \ 1057 defined(CONFIG_SYS_FSL_ERRATUM_A006475) 1058 /* Rechecking the SerDes locks after all SerDes configurations 1059 * are done, As SerDes PLLs may not lock reliably at 5 G VCO 1060 * and at cold temperatures. 1061 * Following sequence ensure the proper locking of SerDes PLLs. 1062 */ 1063 if (SVR_MAJ(get_svr()) == 1) { 1064 if (check_serdes_pll_locks()) 1065 printf("SerDes plls still not locked properly.\n"); 1066 else 1067 printf("SerDes plls have been locked well.\n"); 1068 } 1069 #endif 1070 1071 /* Configure VSC3316 and VSC3308 crossbar switches */ 1072 if (configure_vsc3316_3308()) 1073 printf("VSC:failed to configure VSC3316/3308.\n"); 1074 else 1075 printf("VSC:VSC3316/3308 successfully configured.\n"); 1076 1077 select_i2c_ch_pca(I2C_CH_DEFAULT); 1078 1079 return 0; 1080 } 1081 1082 unsigned long get_board_sys_clk(void) 1083 { 1084 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 1085 1086 switch ((sysclk_conf & 0x0C) >> 2) { 1087 case QIXIS_CLK_100: 1088 return 100000000; 1089 case QIXIS_CLK_125: 1090 return 125000000; 1091 case QIXIS_CLK_133: 1092 return 133333333; 1093 } 1094 return 66666666; 1095 } 1096 1097 unsigned long get_board_ddr_clk(void) 1098 { 1099 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 1100 1101 switch (ddrclk_conf & 0x03) { 1102 case QIXIS_CLK_100: 1103 return 100000000; 1104 case QIXIS_CLK_125: 1105 return 125000000; 1106 case QIXIS_CLK_133: 1107 return 133333333; 1108 } 1109 return 66666666; 1110 } 1111 1112 static int serdes_refclock(u8 sw, u8 sdclk) 1113 { 1114 unsigned int clock; 1115 int ret = -1; 1116 u8 brdcfg4; 1117 1118 if (sdclk == 1) { 1119 brdcfg4 = QIXIS_READ(brdcfg[4]); 1120 if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT) 1121 return SRDS_PLLCR0_RFCK_SEL_125; 1122 else 1123 clock = (sw >> 5) & 7; 1124 } else 1125 clock = (sw >> 6) & 3; 1126 1127 switch (clock) { 1128 case 0: 1129 ret = SRDS_PLLCR0_RFCK_SEL_100; 1130 break; 1131 case 1: 1132 ret = SRDS_PLLCR0_RFCK_SEL_125; 1133 break; 1134 case 2: 1135 ret = SRDS_PLLCR0_RFCK_SEL_156_25; 1136 break; 1137 case 3: 1138 ret = SRDS_PLLCR0_RFCK_SEL_161_13; 1139 break; 1140 case 4: 1141 case 5: 1142 case 6: 1143 ret = SRDS_PLLCR0_RFCK_SEL_122_88; 1144 break; 1145 default: 1146 ret = -1; 1147 break; 1148 } 1149 1150 return ret; 1151 } 1152 1153 #define NUM_SRDS_BANKS 2 1154 1155 int misc_init_r(void) 1156 { 1157 u8 sw; 1158 serdes_corenet_t *srds_regs = 1159 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 1160 u32 actual[NUM_SRDS_BANKS]; 1161 unsigned int i; 1162 int clock; 1163 1164 sw = QIXIS_READ(brdcfg[2]); 1165 clock = serdes_refclock(sw, 1); 1166 if (clock >= 0) 1167 actual[0] = clock; 1168 else 1169 printf("Warning: SDREFCLK1 switch setting is unsupported\n"); 1170 1171 sw = QIXIS_READ(brdcfg[4]); 1172 clock = serdes_refclock(sw, 2); 1173 if (clock >= 0) 1174 actual[1] = clock; 1175 else 1176 printf("Warning: SDREFCLK2 switch setting unsupported\n"); 1177 1178 for (i = 0; i < NUM_SRDS_BANKS; i++) { 1179 u32 pllcr0 = srds_regs->bank[i].pllcr0; 1180 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 1181 if (expected != actual[i]) { 1182 printf("Warning: SERDES bank %u expects reference clock" 1183 " %sMHz, but actual is %sMHz\n", i + 1, 1184 serdes_clock_to_string(expected), 1185 serdes_clock_to_string(actual[i])); 1186 } 1187 } 1188 1189 return 0; 1190 } 1191 1192 int ft_board_setup(void *blob, bd_t *bd) 1193 { 1194 phys_addr_t base; 1195 phys_size_t size; 1196 1197 ft_cpu_setup(blob, bd); 1198 1199 base = env_get_bootm_low(); 1200 size = env_get_bootm_size(); 1201 1202 fdt_fixup_memory(blob, (u64)base, (u64)size); 1203 1204 #ifdef CONFIG_PCI 1205 pci_of_setup(blob, bd); 1206 #endif 1207 1208 fdt_fixup_liodn(blob); 1209 1210 #ifdef CONFIG_HAS_FSL_DR_USB 1211 fsl_fdt_fixup_dr_usb(blob, bd); 1212 #endif 1213 1214 #ifdef CONFIG_SYS_DPAA_FMAN 1215 fdt_fixup_fman_ethernet(blob); 1216 fdt_fixup_board_enet(blob); 1217 #endif 1218 1219 return 0; 1220 } 1221 1222 /* 1223 * Dump board switch settings. 1224 * The bits that cannot be read/sampled via some FPGA or some 1225 * registers, they will be displayed as 1226 * underscore in binary format. mask[] has those bits. 1227 * Some bits are calculated differently than the actual switches 1228 * if booting with overriding by FPGA. 1229 */ 1230 void qixis_dump_switch(void) 1231 { 1232 int i; 1233 u8 sw[5]; 1234 1235 /* 1236 * Any bit with 1 means that bit cannot be reverse engineered. 1237 * It will be displayed as _ in binary format. 1238 */ 1239 static const u8 mask[] = {0x07, 0, 0, 0xff, 0}; 1240 char buf[10]; 1241 u8 brdcfg[16], dutcfg[16]; 1242 1243 for (i = 0; i < 16; i++) { 1244 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); 1245 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); 1246 } 1247 1248 sw[0] = ((brdcfg[0] & 0x0f) << 4) | \ 1249 (brdcfg[9] & 0x08); 1250 sw[1] = ((dutcfg[1] & 0x01) << 7) | \ 1251 ((dutcfg[2] & 0x07) << 4) | \ 1252 ((dutcfg[6] & 0x10) >> 1) | \ 1253 ((dutcfg[6] & 0x80) >> 5) | \ 1254 ((dutcfg[1] & 0x40) >> 5) | \ 1255 (dutcfg[6] & 0x01); 1256 sw[2] = dutcfg[0]; 1257 sw[3] = 0; 1258 sw[4] = ((brdcfg[1] & 0x30) << 2) | \ 1259 ((brdcfg[1] & 0xc0) >> 2) | \ 1260 (brdcfg[1] & 0x0f); 1261 1262 puts("DIP switch settings:\n"); 1263 for (i = 0; i < 5; i++) { 1264 printf("SW%d = 0b%s (0x%02x)\n", 1265 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]); 1266 } 1267 } 1268