1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <i2c.h> 10 #include <netdev.h> 11 #include <linux/compiler.h> 12 #include <asm/mmu.h> 13 #include <asm/processor.h> 14 #include <asm/errno.h> 15 #include <asm/cache.h> 16 #include <asm/immap_85xx.h> 17 #include <asm/fsl_law.h> 18 #include <asm/fsl_serdes.h> 19 #include <asm/fsl_portals.h> 20 #include <asm/fsl_liodn.h> 21 #include <fm_eth.h> 22 23 #include "../common/qixis.h" 24 #include "../common/vsc3316_3308.h" 25 #include "../common/idt8t49n222a_serdes_clk.h" 26 #include "b4860qds.h" 27 #include "b4860qds_qixis.h" 28 #include "b4860qds_crossbar_con.h" 29 30 #define CLK_MUX_SEL_MASK 0x4 31 #define ETH_PHY_CLK_OUT 0x4 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 int checkboard(void) 36 { 37 char buf[64]; 38 u8 sw; 39 struct cpu_type *cpu = gd->arch.cpu; 40 static const char *const freq[] = {"100", "125", "156.25", "161.13", 41 "122.88", "122.88", "122.88"}; 42 int clock; 43 44 printf("Board: %sQDS, ", cpu->name); 45 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", 46 QIXIS_READ(id), QIXIS_READ(arch)); 47 48 sw = QIXIS_READ(brdcfg[0]); 49 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 50 51 if (sw < 0x8) 52 printf("vBank: %d\n", sw); 53 else if (sw >= 0x8 && sw <= 0xE) 54 puts("NAND\n"); 55 else 56 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 57 58 printf("FPGA: v%d (%s), build %d", 59 (int)QIXIS_READ(scver), qixis_read_tag(buf), 60 (int)qixis_read_minor()); 61 /* the timestamp string contains "\n" at the end */ 62 printf(" on %s", qixis_read_time(buf)); 63 64 /* 65 * Display the actual SERDES reference clocks as configured by the 66 * dip switches on the board. Note that the SWx registers could 67 * technically be set to force the reference clocks to match the 68 * values that the SERDES expects (or vice versa). For now, however, 69 * we just display both values and hope the user notices when they 70 * don't match. 71 */ 72 puts("SERDES Reference Clocks: "); 73 sw = QIXIS_READ(brdcfg[2]); 74 clock = (sw >> 5) & 7; 75 printf("Bank1=%sMHz ", freq[clock]); 76 sw = QIXIS_READ(brdcfg[4]); 77 clock = (sw >> 6) & 3; 78 printf("Bank2=%sMHz\n", freq[clock]); 79 80 return 0; 81 } 82 83 int select_i2c_ch_pca(u8 ch) 84 { 85 int ret; 86 87 /* Selecting proper channel via PCA*/ 88 ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1); 89 if (ret) { 90 printf("PCA: failed to select proper channel.\n"); 91 return ret; 92 } 93 94 return 0; 95 } 96 97 int configure_vsc3316_3308(void) 98 { 99 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 100 unsigned int num_vsc16_con, num_vsc08_con; 101 u32 serdes1_prtcl, serdes2_prtcl; 102 int ret; 103 104 serdes1_prtcl = in_be32(&gur->rcwsr[4]) & 105 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 106 if (!serdes1_prtcl) { 107 printf("SERDES1 is not enabled\n"); 108 return 0; 109 } 110 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 111 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); 112 113 serdes2_prtcl = in_be32(&gur->rcwsr[4]) & 114 FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 115 if (!serdes2_prtcl) { 116 printf("SERDES2 is not enabled\n"); 117 return 0; 118 } 119 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 120 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); 121 122 switch (serdes1_prtcl) { 123 case 0x29: 124 case 0x2a: 125 case 0x2C: 126 case 0x2D: 127 case 0x2E: 128 /* 129 * Configuration: 130 * SERDES: 1 131 * Lanes: A,B: SGMII 132 * Lanes: C,D,E,F,G,H: CPRI 133 */ 134 debug("Configuring crossbar to use onboard SGMII PHYs:" 135 "srds_prctl:%x\n", serdes1_prtcl); 136 num_vsc16_con = NUM_CON_VSC3316; 137 /* Configure VSC3316 crossbar switch */ 138 ret = select_i2c_ch_pca(I2C_CH_VSC3316); 139 if (!ret) { 140 ret = vsc3316_config(VSC3316_TX_ADDRESS, 141 vsc16_tx_4sfp_sgmii_12_56, 142 num_vsc16_con); 143 if (ret) 144 return ret; 145 ret = vsc3316_config(VSC3316_RX_ADDRESS, 146 vsc16_rx_4sfp_sgmii_12_56, 147 num_vsc16_con); 148 if (ret) 149 return ret; 150 } else { 151 return ret; 152 } 153 break; 154 155 case 0x02: 156 case 0x04: 157 case 0x05: 158 case 0x06: 159 case 0x08: 160 case 0x09: 161 case 0x0A: 162 case 0x0B: 163 case 0x0C: 164 case 0x30: 165 case 0x32: 166 case 0x33: 167 case 0x34: 168 case 0x39: 169 case 0x3A: 170 case 0x3C: 171 case 0x3D: 172 case 0x5C: 173 case 0x5D: 174 /* 175 * Configuration: 176 * SERDES: 1 177 * Lanes: A,B: AURORA 178 * Lanes: C,d: SGMII 179 * Lanes: E,F,G,H: CPRI 180 */ 181 debug("Configuring crossbar for Aurora, SGMII 3 and 4," 182 " and CPRI. srds_prctl:%x\n", serdes1_prtcl); 183 num_vsc16_con = NUM_CON_VSC3316; 184 /* Configure VSC3316 crossbar switch */ 185 ret = select_i2c_ch_pca(I2C_CH_VSC3316); 186 if (!ret) { 187 ret = vsc3316_config(VSC3316_TX_ADDRESS, 188 vsc16_tx_sfp_sgmii_aurora, 189 num_vsc16_con); 190 if (ret) 191 return ret; 192 ret = vsc3316_config(VSC3316_RX_ADDRESS, 193 vsc16_rx_sfp_sgmii_aurora, 194 num_vsc16_con); 195 if (ret) 196 return ret; 197 } else { 198 return ret; 199 } 200 break; 201 202 #ifdef CONFIG_PPC_B4420 203 case 0x17: 204 case 0x18: 205 /* 206 * Configuration: 207 * SERDES: 1 208 * Lanes: A,B,C,D: SGMII 209 * Lanes: E,F,G,H: CPRI 210 */ 211 debug("Configuring crossbar to use onboard SGMII PHYs:" 212 "srds_prctl:%x\n", serdes1_prtcl); 213 num_vsc16_con = NUM_CON_VSC3316; 214 /* Configure VSC3316 crossbar switch */ 215 ret = select_i2c_ch_pca(I2C_CH_VSC3316); 216 if (!ret) { 217 ret = vsc3316_config(VSC3316_TX_ADDRESS, 218 vsc16_tx_sgmii_lane_cd, num_vsc16_con); 219 if (ret) 220 return ret; 221 ret = vsc3316_config(VSC3316_RX_ADDRESS, 222 vsc16_rx_sgmii_lane_cd, num_vsc16_con); 223 if (ret) 224 return ret; 225 } else { 226 return ret; 227 } 228 break; 229 #endif 230 231 case 0x3E: 232 case 0x0D: 233 case 0x0E: 234 case 0x12: 235 num_vsc16_con = NUM_CON_VSC3316; 236 /* Configure VSC3316 crossbar switch */ 237 ret = select_i2c_ch_pca(I2C_CH_VSC3316); 238 if (!ret) { 239 ret = vsc3316_config(VSC3316_TX_ADDRESS, 240 vsc16_tx_sfp, num_vsc16_con); 241 if (ret) 242 return ret; 243 ret = vsc3316_config(VSC3316_RX_ADDRESS, 244 vsc16_rx_sfp, num_vsc16_con); 245 if (ret) 246 return ret; 247 } else { 248 return ret; 249 } 250 break; 251 default: 252 printf("WARNING:VSC crossbars programming not supported for:%x" 253 " SerDes1 Protocol.\n", serdes1_prtcl); 254 return -1; 255 } 256 257 switch (serdes2_prtcl) { 258 case 0x9E: 259 case 0x9A: 260 case 0x98: 261 case 0xb2: 262 case 0x49: 263 case 0x4E: 264 case 0x8D: 265 case 0x7A: 266 num_vsc08_con = NUM_CON_VSC3308; 267 /* Configure VSC3308 crossbar switch */ 268 ret = select_i2c_ch_pca(I2C_CH_VSC3308); 269 if (!ret) { 270 ret = vsc3308_config(VSC3308_TX_ADDRESS, 271 vsc08_tx_amc, num_vsc08_con); 272 if (ret) 273 return ret; 274 ret = vsc3308_config(VSC3308_RX_ADDRESS, 275 vsc08_rx_amc, num_vsc08_con); 276 if (ret) 277 return ret; 278 } else { 279 return ret; 280 } 281 break; 282 default: 283 printf("WARNING:VSC crossbars programming not supported for: %x" 284 " SerDes2 Protocol.\n", serdes2_prtcl); 285 return -1; 286 } 287 288 return 0; 289 } 290 291 static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num) 292 { 293 u32 rst_err; 294 295 /* Steps For SerDes PLLs reset and reconfiguration 296 * or PLL power-up procedure 297 */ 298 debug("CALIBRATE PLL:%d\n", pll_num); 299 clrbits_be32(&srds_regs->bank[pll_num].rstctl, 300 SRDS_RSTCTL_SDRST_B); 301 udelay(10); 302 clrbits_be32(&srds_regs->bank[pll_num].rstctl, 303 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); 304 udelay(10); 305 setbits_be32(&srds_regs->bank[pll_num].rstctl, 306 SRDS_RSTCTL_RST); 307 setbits_be32(&srds_regs->bank[pll_num].rstctl, 308 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B 309 | SRDS_RSTCTL_SDRST_B)); 310 311 udelay(20); 312 313 /* Check whether PLL has been locked or not */ 314 rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) & 315 SRDS_RSTCTL_RSTERR; 316 rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT; 317 debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err); 318 if (rst_err) 319 return rst_err; 320 321 return rst_err; 322 } 323 324 static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num) 325 { 326 int ret = 0; 327 u32 fcap, dcbias, bcap, pllcr1, pllcr0; 328 329 if (calibrate_pll(srds_regs, pll_num)) { 330 /* STEP 1 */ 331 /* Read fcap, dcbias and bcap value */ 332 clrbits_be32(&srds_regs->bank[pll_num].pllcr0, 333 SRDS_PLLCR0_DCBIAS_OUT_EN); 334 fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) & 335 SRDS_PLLSR2_FCAP; 336 fcap >>= SRDS_PLLSR2_FCAP_SHIFT; 337 bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) & 338 SRDS_PLLSR2_BCAP_EN; 339 bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT; 340 setbits_be32(&srds_regs->bank[pll_num].pllcr0, 341 SRDS_PLLCR0_DCBIAS_OUT_EN); 342 dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) & 343 SRDS_PLLSR2_DCBIAS; 344 dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT; 345 debug("values of bcap:%x, fcap:%x and dcbias:%x\n", 346 bcap, fcap, dcbias); 347 if (fcap == 0 && bcap == 1) { 348 /* Step 3 */ 349 clrbits_be32(&srds_regs->bank[pll_num].rstctl, 350 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B 351 | SRDS_RSTCTL_SDRST_B)); 352 clrbits_be32(&srds_regs->bank[pll_num].pllcr1, 353 SRDS_PLLCR1_BCAP_EN); 354 setbits_be32(&srds_regs->bank[pll_num].pllcr1, 355 SRDS_PLLCR1_BCAP_OVD); 356 if (calibrate_pll(srds_regs, pll_num)) { 357 /*save the fcap, dcbias and bcap values*/ 358 clrbits_be32(&srds_regs->bank[pll_num].pllcr0, 359 SRDS_PLLCR0_DCBIAS_OUT_EN); 360 fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) 361 & SRDS_PLLSR2_FCAP; 362 fcap >>= SRDS_PLLSR2_FCAP_SHIFT; 363 bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) 364 & SRDS_PLLSR2_BCAP_EN; 365 bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT; 366 setbits_be32(&srds_regs->bank[pll_num].pllcr0, 367 SRDS_PLLCR0_DCBIAS_OUT_EN); 368 dcbias = in_be32 369 (&srds_regs->bank[pll_num].pllsr2) & 370 SRDS_PLLSR2_DCBIAS; 371 dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT; 372 373 /* Step 4*/ 374 clrbits_be32(&srds_regs->bank[pll_num].rstctl, 375 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B 376 | SRDS_RSTCTL_SDRST_B)); 377 setbits_be32(&srds_regs->bank[pll_num].pllcr1, 378 SRDS_PLLCR1_BYP_CAL); 379 clrbits_be32(&srds_regs->bank[pll_num].pllcr1, 380 SRDS_PLLCR1_BCAP_EN); 381 setbits_be32(&srds_regs->bank[pll_num].pllcr1, 382 SRDS_PLLCR1_BCAP_OVD); 383 /* change the fcap and dcbias to the saved 384 * values from Step 3 */ 385 clrbits_be32(&srds_regs->bank[pll_num].pllcr1, 386 SRDS_PLLCR1_PLL_FCAP); 387 pllcr1 = (in_be32 388 (&srds_regs->bank[pll_num].pllcr1)| 389 (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT)); 390 out_be32(&srds_regs->bank[pll_num].pllcr1, 391 pllcr1); 392 clrbits_be32(&srds_regs->bank[pll_num].pllcr0, 393 SRDS_PLLCR0_DCBIAS_OVRD); 394 pllcr0 = (in_be32 395 (&srds_regs->bank[pll_num].pllcr0)| 396 (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT)); 397 out_be32(&srds_regs->bank[pll_num].pllcr0, 398 pllcr0); 399 ret = calibrate_pll(srds_regs, pll_num); 400 if (ret) 401 return ret; 402 } else { 403 goto out; 404 } 405 } else { /* Step 5 */ 406 clrbits_be32(&srds_regs->bank[pll_num].rstctl, 407 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B 408 | SRDS_RSTCTL_SDRST_B)); 409 udelay(10); 410 /* Change the fcap, dcbias, and bcap to the 411 * values from Step 1 */ 412 setbits_be32(&srds_regs->bank[pll_num].pllcr1, 413 SRDS_PLLCR1_BYP_CAL); 414 clrbits_be32(&srds_regs->bank[pll_num].pllcr1, 415 SRDS_PLLCR1_PLL_FCAP); 416 pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)| 417 (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT)); 418 out_be32(&srds_regs->bank[pll_num].pllcr1, 419 pllcr1); 420 clrbits_be32(&srds_regs->bank[pll_num].pllcr0, 421 SRDS_PLLCR0_DCBIAS_OVRD); 422 pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)| 423 (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT)); 424 out_be32(&srds_regs->bank[pll_num].pllcr0, 425 pllcr0); 426 clrbits_be32(&srds_regs->bank[pll_num].pllcr1, 427 SRDS_PLLCR1_BCAP_EN); 428 setbits_be32(&srds_regs->bank[pll_num].pllcr1, 429 SRDS_PLLCR1_BCAP_OVD); 430 ret = calibrate_pll(srds_regs, pll_num); 431 if (ret) 432 return ret; 433 } 434 } 435 out: 436 return 0; 437 } 438 439 static int check_serdes_pll_locks(void) 440 { 441 serdes_corenet_t *srds1_regs = 442 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 443 serdes_corenet_t *srds2_regs = 444 (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR; 445 int i, ret1, ret2; 446 447 debug("\nSerDes1 Lock check\n"); 448 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { 449 ret1 = check_pll_locks(srds1_regs, i); 450 if (ret1) { 451 printf("SerDes1, PLL:%d didnt lock\n", i); 452 return ret1; 453 } 454 } 455 debug("\nSerDes2 Lock check\n"); 456 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { 457 ret2 = check_pll_locks(srds2_regs, i); 458 if (ret2) { 459 printf("SerDes2, PLL:%d didnt lock\n", i); 460 return ret2; 461 } 462 } 463 464 return 0; 465 } 466 467 int config_serdes1_refclks(void) 468 { 469 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 470 serdes_corenet_t *srds_regs = 471 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 472 u32 serdes1_prtcl, lane; 473 unsigned int flag_sgmii_aurora_prtcl = 0; 474 int i; 475 int ret = 0; 476 477 serdes1_prtcl = in_be32(&gur->rcwsr[4]) & 478 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 479 if (!serdes1_prtcl) { 480 printf("SERDES1 is not enabled\n"); 481 return -1; 482 } 483 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 484 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); 485 486 /* To prevent generation of reset request from SerDes 487 * while changing the refclks, By setting SRDS_RST_MSK bit, 488 * SerDes reset event cannot cause a reset request 489 */ 490 setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); 491 492 /* Reconfigure IDT idt8t49n222a device for CPRI to work 493 * For this SerDes1's Refclk1 and refclk2 need to be set 494 * to 122.88MHz 495 */ 496 switch (serdes1_prtcl) { 497 case 0x2A: 498 case 0x2C: 499 case 0x2D: 500 case 0x2E: 501 case 0x02: 502 case 0x04: 503 case 0x05: 504 case 0x06: 505 case 0x08: 506 case 0x09: 507 case 0x0A: 508 case 0x0B: 509 case 0x0C: 510 case 0x30: 511 case 0x32: 512 case 0x33: 513 case 0x34: 514 case 0x39: 515 case 0x3A: 516 case 0x3C: 517 case 0x3D: 518 case 0x5C: 519 case 0x5D: 520 debug("Configuring idt8t49n222a for CPRI SerDes clks:" 521 " for srds_prctl:%x\n", serdes1_prtcl); 522 ret = select_i2c_ch_pca(I2C_CH_IDT); 523 if (!ret) { 524 ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1, 525 SERDES_REFCLK_122_88, 526 SERDES_REFCLK_122_88, 0); 527 if (ret) { 528 printf("IDT8T49N222A configuration failed.\n"); 529 goto out; 530 } else 531 debug("IDT8T49N222A configured.\n"); 532 } else { 533 goto out; 534 } 535 select_i2c_ch_pca(I2C_CH_DEFAULT); 536 537 /* Change SerDes1's Refclk1 to 125MHz for on board 538 * SGMIIs or Aurora to work 539 */ 540 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 541 enum srds_prtcl lane_prtcl = serdes_get_prtcl 542 (0, serdes1_prtcl, lane); 543 switch (lane_prtcl) { 544 case SGMII_FM1_DTSEC1: 545 case SGMII_FM1_DTSEC2: 546 case SGMII_FM1_DTSEC3: 547 case SGMII_FM1_DTSEC4: 548 case SGMII_FM1_DTSEC5: 549 case SGMII_FM1_DTSEC6: 550 case AURORA: 551 flag_sgmii_aurora_prtcl++; 552 break; 553 default: 554 break; 555 } 556 } 557 558 if (flag_sgmii_aurora_prtcl) 559 QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); 560 561 /* Steps For SerDes PLLs reset and reconfiguration after 562 * changing SerDes's refclks 563 */ 564 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { 565 debug("For PLL%d reset and reconfiguration after" 566 " changing refclks\n", i+1); 567 clrbits_be32(&srds_regs->bank[i].rstctl, 568 SRDS_RSTCTL_SDRST_B); 569 udelay(10); 570 clrbits_be32(&srds_regs->bank[i].rstctl, 571 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); 572 udelay(10); 573 setbits_be32(&srds_regs->bank[i].rstctl, 574 SRDS_RSTCTL_RST); 575 setbits_be32(&srds_regs->bank[i].rstctl, 576 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B 577 | SRDS_RSTCTL_SDRST_B)); 578 } 579 break; 580 default: 581 printf("WARNING:IDT8T49N222A configuration not" 582 " supported for:%x SerDes1 Protocol.\n", 583 serdes1_prtcl); 584 } 585 586 out: 587 /* Clearing SRDS_RST_MSK bit as now 588 * SerDes reset event can cause a reset request 589 */ 590 clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); 591 return ret; 592 } 593 594 int config_serdes2_refclks(void) 595 { 596 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 597 serdes_corenet_t *srds2_regs = 598 (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR; 599 u32 serdes2_prtcl; 600 int ret = 0; 601 int i; 602 603 serdes2_prtcl = in_be32(&gur->rcwsr[4]) & 604 FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 605 if (!serdes2_prtcl) { 606 debug("SERDES2 is not enabled\n"); 607 return -ENODEV; 608 } 609 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 610 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); 611 612 /* To prevent generation of reset request from SerDes 613 * while changing the refclks, By setting SRDS_RST_MSK bit, 614 * SerDes reset event cannot cause a reset request 615 */ 616 setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); 617 618 /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work 619 * For this SerDes2's Refclk1 need to be set to 100MHz 620 */ 621 switch (serdes2_prtcl) { 622 case 0x9E: 623 case 0x9A: 624 case 0xb2: 625 debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n", 626 serdes2_prtcl); 627 ret = select_i2c_ch_pca(I2C_CH_IDT); 628 if (!ret) { 629 ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2, 630 SERDES_REFCLK_100, 631 SERDES_REFCLK_156_25, 0); 632 if (ret) { 633 printf("IDT8T49N222A configuration failed.\n"); 634 goto out; 635 } else 636 debug("IDT8T49N222A configured.\n"); 637 } else { 638 goto out; 639 } 640 select_i2c_ch_pca(I2C_CH_DEFAULT); 641 642 /* Steps For SerDes PLLs reset and reconfiguration after 643 * changing SerDes's refclks 644 */ 645 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { 646 clrbits_be32(&srds2_regs->bank[i].rstctl, 647 SRDS_RSTCTL_SDRST_B); 648 udelay(10); 649 clrbits_be32(&srds2_regs->bank[i].rstctl, 650 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); 651 udelay(10); 652 setbits_be32(&srds2_regs->bank[i].rstctl, 653 SRDS_RSTCTL_RST); 654 setbits_be32(&srds2_regs->bank[i].rstctl, 655 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B 656 | SRDS_RSTCTL_SDRST_B)); 657 658 udelay(10); 659 } 660 break; 661 default: 662 printf("IDT configuration not supported for:%x S2 Protocol.\n", 663 serdes2_prtcl); 664 } 665 666 out: 667 /* Clearing SRDS_RST_MSK bit as now 668 * SerDes reset event can cause a reset request 669 */ 670 clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); 671 return ret; 672 } 673 674 int board_early_init_r(void) 675 { 676 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 677 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 678 int ret; 679 680 /* 681 * Remap Boot flash + PROMJET region to caching-inhibited 682 * so that flash can be erased properly. 683 */ 684 685 /* Flush d-cache and invalidate i-cache of any FLASH data */ 686 flush_dcache(); 687 invalidate_icache(); 688 689 /* invalidate existing TLB entry for flash + promjet */ 690 disable_tlb(flash_esel); 691 692 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 693 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 694 0, flash_esel, BOOKE_PAGESZ_256M, 1); 695 696 set_liodns(); 697 #ifdef CONFIG_SYS_DPAA_QBMAN 698 setup_portals(); 699 #endif 700 /* SerDes1 refclks need to be set again, as default clks 701 * are not suitable for CPRI and onboard SGMIIs to work 702 * simultaneously. 703 * This function will set SerDes1's Refclk1 and refclk2 704 * as per SerDes1 protocols 705 */ 706 if (config_serdes1_refclks()) 707 printf("SerDes1 Refclks couldn't set properly.\n"); 708 else 709 printf("SerDes1 Refclks have been set.\n"); 710 711 /* SerDes2 refclks need to be set again, as default clks 712 * are not suitable for PCIe SATA to work 713 * This function will set SerDes2's Refclk1 and refclk2 714 * for SerDes2 protocols having PCIe in them 715 * for PCIe SATA to work 716 */ 717 ret = config_serdes2_refclks(); 718 if (!ret) 719 printf("SerDes2 Refclks have been set.\n"); 720 else if (ret == -ENODEV) 721 printf("SerDes disable, Refclks couldn't change.\n"); 722 else 723 printf("SerDes2 Refclk reconfiguring failed.\n"); 724 725 #if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \ 726 defined(CONFIG_SYS_FSL_ERRATUM_A006475) 727 /* Rechecking the SerDes locks after all SerDes configurations 728 * are done, As SerDes PLLs may not lock reliably at 5 G VCO 729 * and at cold temperatures. 730 * Following sequence ensure the proper locking of SerDes PLLs. 731 */ 732 if (SVR_MAJ(get_svr()) == 1) { 733 if (check_serdes_pll_locks()) 734 printf("SerDes plls still not locked properly.\n"); 735 else 736 printf("SerDes plls have been locked well.\n"); 737 } 738 #endif 739 740 /* Configure VSC3316 and VSC3308 crossbar switches */ 741 if (configure_vsc3316_3308()) 742 printf("VSC:failed to configure VSC3316/3308.\n"); 743 else 744 printf("VSC:VSC3316/3308 successfully configured.\n"); 745 746 select_i2c_ch_pca(I2C_CH_DEFAULT); 747 748 return 0; 749 } 750 751 unsigned long get_board_sys_clk(void) 752 { 753 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 754 755 switch ((sysclk_conf & 0x0C) >> 2) { 756 case QIXIS_CLK_100: 757 return 100000000; 758 case QIXIS_CLK_125: 759 return 125000000; 760 case QIXIS_CLK_133: 761 return 133333333; 762 } 763 return 66666666; 764 } 765 766 unsigned long get_board_ddr_clk(void) 767 { 768 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 769 770 switch (ddrclk_conf & 0x03) { 771 case QIXIS_CLK_100: 772 return 100000000; 773 case QIXIS_CLK_125: 774 return 125000000; 775 case QIXIS_CLK_133: 776 return 133333333; 777 } 778 return 66666666; 779 } 780 781 static int serdes_refclock(u8 sw, u8 sdclk) 782 { 783 unsigned int clock; 784 int ret = -1; 785 u8 brdcfg4; 786 787 if (sdclk == 1) { 788 brdcfg4 = QIXIS_READ(brdcfg[4]); 789 if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT) 790 return SRDS_PLLCR0_RFCK_SEL_125; 791 else 792 clock = (sw >> 5) & 7; 793 } else 794 clock = (sw >> 6) & 3; 795 796 switch (clock) { 797 case 0: 798 ret = SRDS_PLLCR0_RFCK_SEL_100; 799 break; 800 case 1: 801 ret = SRDS_PLLCR0_RFCK_SEL_125; 802 break; 803 case 2: 804 ret = SRDS_PLLCR0_RFCK_SEL_156_25; 805 break; 806 case 3: 807 ret = SRDS_PLLCR0_RFCK_SEL_161_13; 808 break; 809 case 4: 810 case 5: 811 case 6: 812 ret = SRDS_PLLCR0_RFCK_SEL_122_88; 813 break; 814 default: 815 ret = -1; 816 break; 817 } 818 819 return ret; 820 } 821 822 #define NUM_SRDS_BANKS 2 823 824 int misc_init_r(void) 825 { 826 u8 sw; 827 serdes_corenet_t *srds_regs = 828 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 829 u32 actual[NUM_SRDS_BANKS]; 830 unsigned int i; 831 int clock; 832 833 sw = QIXIS_READ(brdcfg[2]); 834 clock = serdes_refclock(sw, 1); 835 if (clock >= 0) 836 actual[0] = clock; 837 else 838 printf("Warning: SDREFCLK1 switch setting is unsupported\n"); 839 840 sw = QIXIS_READ(brdcfg[4]); 841 clock = serdes_refclock(sw, 2); 842 if (clock >= 0) 843 actual[1] = clock; 844 else 845 printf("Warning: SDREFCLK2 switch setting unsupported\n"); 846 847 for (i = 0; i < NUM_SRDS_BANKS; i++) { 848 u32 pllcr0 = srds_regs->bank[i].pllcr0; 849 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 850 if (expected != actual[i]) { 851 printf("Warning: SERDES bank %u expects reference clock" 852 " %sMHz, but actual is %sMHz\n", i + 1, 853 serdes_clock_to_string(expected), 854 serdes_clock_to_string(actual[i])); 855 } 856 } 857 858 return 0; 859 } 860 861 void ft_board_setup(void *blob, bd_t *bd) 862 { 863 phys_addr_t base; 864 phys_size_t size; 865 866 ft_cpu_setup(blob, bd); 867 868 base = getenv_bootm_low(); 869 size = getenv_bootm_size(); 870 871 fdt_fixup_memory(blob, (u64)base, (u64)size); 872 873 #ifdef CONFIG_PCI 874 pci_of_setup(blob, bd); 875 #endif 876 877 fdt_fixup_liodn(blob); 878 879 #ifdef CONFIG_HAS_FSL_DR_USB 880 fdt_fixup_dr_usb(blob, bd); 881 #endif 882 883 #ifdef CONFIG_SYS_DPAA_FMAN 884 fdt_fixup_fman_ethernet(blob); 885 fdt_fixup_board_enet(blob); 886 #endif 887 } 888 889 /* 890 * Dump board switch settings. 891 * The bits that cannot be read/sampled via some FPGA or some 892 * registers, they will be displayed as 893 * underscore in binary format. mask[] has those bits. 894 * Some bits are calculated differently than the actual switches 895 * if booting with overriding by FPGA. 896 */ 897 void qixis_dump_switch(void) 898 { 899 int i; 900 u8 sw[5]; 901 902 /* 903 * Any bit with 1 means that bit cannot be reverse engineered. 904 * It will be displayed as _ in binary format. 905 */ 906 static const u8 mask[] = {0x07, 0, 0, 0xff, 0}; 907 char buf[10]; 908 u8 brdcfg[16], dutcfg[16]; 909 910 for (i = 0; i < 16; i++) { 911 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); 912 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); 913 } 914 915 sw[0] = ((brdcfg[0] & 0x0f) << 4) | \ 916 (brdcfg[9] & 0x08); 917 sw[1] = ((dutcfg[1] & 0x01) << 7) | \ 918 ((dutcfg[2] & 0x07) << 4) | \ 919 ((dutcfg[6] & 0x10) >> 1) | \ 920 ((dutcfg[6] & 0x80) >> 5) | \ 921 ((dutcfg[1] & 0x40) >> 5) | \ 922 (dutcfg[6] & 0x01); 923 sw[2] = dutcfg[0]; 924 sw[3] = 0; 925 sw[4] = ((brdcfg[1] & 0x30) << 2) | \ 926 ((brdcfg[1] & 0xc0) >> 2) | \ 927 (brdcfg[1] & 0x0f); 928 929 puts("DIP switch settings:\n"); 930 for (i = 0; i < 5; i++) { 931 printf("SW%d = 0b%s (0x%02x)\n", 932 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]); 933 } 934 } 935