1/* 2 * Copyright (C) 2009 Renesas Solutions Corp. 3 * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 4 * 5 * board/espt/lowlevel_init.S 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23#include <config.h> 24#include <version.h> 25#include <asm/processor.h> 26#include <asm/macro.h> 27 28 .global lowlevel_init 29 30 .text 31 .align 2 32 33lowlevel_init: 34 35 write32 WDTCSR_A, WDTCSR_D 36 37 write32 WDTST_A, WDTST_D 38 39 write32 WDTBST_A, WDTBST_D 40 41 write32 CCR_A, CCR_CACHE_ICI_D 42 43 write32 MMUCR_A, MMU_CONTROL_TI_D 44 45 write32 MSTPCR0_A, MSTPCR0_D 46 47 write32 MSTPCR1_A, MSTPCR1_D 48 49 write32 RAMCR_A, RAMCR_D 50 51 /* 52 * Setting infomation from 53 * original ESPT-GIGA bootloader register 54 */ 55 write32 MMSEL_A, MMSEL_D 56 57 /* dummy */ 58 mov.l @r1, r2 59 mov.l @r1, r2 60 synco 61 62 write32 BCR_A, BCR_D 63 64 write32 CS0BCR_A, CS0BCR_D 65 66 write32 CS0WCR_A, CS0WCR_D 67 68 /* 69 * DDR-SDRAM setting 70 */ 71 72 /* set DDR-SDRAM dummy read */ 73 write32 MMSEL_A, MMSEL_D 74 75 write32 MMSEL_A, CS0_A 76 77 /* set DDR-SDRAM bus/endian etc */ 78 write32 MIM_U_A, MIM_U_D 79 80 write32 MIM_L_A, MIM_L_D0 81 82 write32 SDR_L_A, SDR_L_A_D0 83 84 write32 STR_L_A, STR_L_A_D0 85 86 /* DDR-SDRAM access control */ 87 write32 MIM_L_A, MIM_L_D1 88 89 write32 SCR_L_A, SCR_L_A_D0 90 91 write32 SCR_L_A, SCR_L_A_D1 92 93 write32 EMRS_A, EMRS_D 94 95 write32 MRS1_A, MRS1_D 96 97 write32 MIM_U_A, MIM_U_D 98 99 write32 MIM_L_A, MIM_L_A_D2 100 101 write32 SCR_L_A, SCR_L_A_D2 102 103 write32 SCR_L_A, SCR_L_A_D2 104 105 write32 MRS2_A, MRS2_D 106 107 /* wait 200us */ 108 wait_timer REPEAT_R3 109 110 /* GPIO setting */ 111 write16 PSEL0_A, PSEL0_D 112 113 write16 PSEL1_A, PSEL1_D 114 115 write16 PSEL2_A, PSEL2_D 116 117 write16 PSEL3_A, PSEL3_D 118 119 write16 PSEL4_A, PSEL4_D 120 121 write8 PADR_A, PADR_D 122 123 write16 PACR_A, PACR_D 124 125 write8 PBDR_A, PBDR_D 126 127 write16 PBCR_A, PBCR_D 128 129 write8 PCDR_A, PCDR_D 130 131 write16 PCCR_A, PCCR_D 132 133 write8 PDDR_A, PDDR_D 134 135 write16 PDCR_A, PDCR_D 136 137 write16 PECR_A, PECR_D 138 139 write16 PFCR_A, PFCR_D 140 141 write16 PGCR_A, PGCR_D 142 143 write16 PHCR_A, PHCR_D 144 145 write16 PICR_A, PICR_D 146 147 write8 PJDR_A, PJDR_D 148 149 write16 PJCR_A, PJCR_D 150 151 /* wait 50us */ 152 wait_timer REPEAT_R3 153 154 write8 PKDR_A, PKDR_D 155 156 write16 PKCR_A, PKCR_D 157 158 write16 PLCR_A, PLCR_D 159 160 write16 PMCR_A, PMCR_D 161 162 write16 PNCR_A, PNCR_D 163 164 write16 POCR_A, POCR_D 165 166 167 /* ICR0 ,ICR1 */ 168 write32 ICR0_A, ICR0_D 169 170 write32 ICR1_A, ICR1_D 171 172 /* USB Host */ 173 write32 USB_USBHSC_A, USB_USBHSC_D 174 175 write32 CCR_A, CCR_CACHE_D_2 176 177 rts 178 nop 179 180 .align 2 181 182/* GPIO Crontrol Register */ 183PACR_A: .long 0xFFEF0000 184PBCR_A: .long 0xFFEF0002 185PCCR_A: .long 0xFFEF0004 186PDCR_A: .long 0xFFEF0006 187PECR_A: .long 0xFFEF0008 188PFCR_A: .long 0xFFEF000A 189PGCR_A: .long 0xFFEF000C 190PHCR_A: .long 0xFFEF000E 191PICR_A: .long 0xFFEF0010 192PJCR_A: .long 0xFFEF0012 193PKCR_A: .long 0xFFEF0014 194PLCR_A: .long 0xFFEF0016 195PMCR_A: .long 0xFFEF0018 196PNCR_A: .long 0xFFEF001A 197POCR_A: .long 0xFFEF001C 198 199/* GPIO Data Register */ 200PADR_A: .long 0xFFEF0020 201PBDR_A: .long 0xFFEF0022 202PCDR_A: .long 0xFFEF0024 203PDDR_A: .long 0xFFEF0026 204PJDR_A: .long 0xFFEF0032 205PKDR_A: .long 0xFFEF0034 206 207/* GPIO Set data */ 208PADR_D: .long 0x00000000 209PACR_D: .long 0x00001400 210PBDR_D: .long 0x00000000 211PBCR_D: .long 0x0000555A 212PCDR_D: .long 0x00000000 213PCCR_D: .long 0x00005555 214PDDR_D: .long 0x00000000 215PDCR_D: .long 0x00000155 216PECR_D: .long 0x00000000 217PFCR_D: .long 0x00000000 218PGCR_D: .long 0x00000000 219PHCR_D: .long 0x00000000 220PICR_D: .long 0x00000800 221PJDR_D: .long 0x00000006 222PJCR_D: .long 0x00005A57 223PKDR_D: .long 0x00000000 224PKCR_D: .long 0x0000FFF9 225PLCR_D: .long 0x0000C330 226PMCR_D: .long 0x0000FFFF 227PNCR_D: .long 0x00000242 228POCR_D: .long 0x00000000 229 230/* Pin Select */ 231PSEL0_A: .long 0xFFEF0070 232PSEL1_A: .long 0xFFEF0072 233PSEL2_A: .long 0xFFEF0074 234PSEL3_A: .long 0xFFEF0076 235PSEL4_A: .long 0xFFEF0078 236PSEL0_D: .long 0x0001 237PSEL1_D: .long 0x2400 238PSEL2_D: .long 0x0000 239PSEL3_D: .long 0x2421 240PSEL4_D: .long 0x0000 241 242MMSEL_A: .long 0xFE600020 243BCR_A: .long 0xFF801000 244CS0BCR_A: .long 0xFF802000 245CS0WCR_A: .long 0xFF802008 246ICR0_A: .long 0xFFD00000 247ICR1_A: .long 0xFFD0001C 248 249MMSEL_D: .long 0xA5A50000 250BCR_D: .long 0x05000000 251CS0BCR_D: .long 0x232306F0 252CS0WCR_D: .long 0x00011104 253ICR0_D: .long 0x80C00000 254ICR1_D: .long 0x00020000 255 256/* RWBT Address */ 257WDTST_A: .long 0xFFCC0000 258WDTCSR_A: .long 0xFFCC0004 259WDTBST_A: .long 0xFFCC0008 260/* RWBT Data */ 261WDTST_D: .long 0x5A000FFF 262WDTCSR_D: .long 0xA5000000 263WDTBST_D: .long 0x55000000 264 265/* Cache Address */ 266CCR_A: .long 0xFF00001C 267MMUCR_A: .long 0xFF000010 268RAMCR_A: .long 0xFF000074 269 270/* Cache Data */ 271CCR_CACHE_ICI_D:.long 0x00000800 272CCR_CACHE_D_2: .long 0x00000103 273MMU_CONTROL_TI_D:.long 0x00000004 274RAMCR_D: .long 0x00000200 275 276/* Low power mode control Address */ 277MSTPCR0_A: .long 0xFFC80030 278MSTPCR1_A: .long 0xFFC80038 279/* Low power mode control Data */ 280MSTPCR0_D: .long 0x00000000 281MSTPCR1_D: .long 0x00000000 282 283REPEAT0_R3: .long 0x00002000 284REPEAT_R3: .long 0x00000200 285CS0_A: .long 0xA8000000 286 287MIM_U_A: .long 0xFE800008 288MIM_L_A: .long 0xFE80000C 289SCR_U_A: .long 0xFE800010 290SCR_L_A: .long 0xFE800014 291STR_U_A: .long 0xFE800018 292STR_L_A: .long 0xFE80001C 293SDR_U_A: .long 0xFE800030 294SDR_L_A: .long 0xFE800034 295EMRS_A: .long 0xFE902000 296MRS1_A: .long 0xFE900B08 297MRS2_A: .long 0xFE900308 298 299MIM_U_D: .long 0x00000000 300MIM_L_D0: .long 0x04100008 301MIM_L_D1: .long 0x02EE0009 302MIM_L_D2: .long 0x02EE0209 303 304SDR_L_A_D0: .long 0x00000300 305STR_L_A_D0: .long 0x00010040 306MIM_L_A_D1: .long 0x04100009 307SCR_L_A_D0: .long 0x00000003 308SCR_L_A_D1: .long 0x00000002 309MIM_L_A_D2: .long 0x04100209 310SCR_L_A_D2: .long 0x00000004 311 312SCR_L_NORMAL: .long 0x00000000 313SCR_L_NOP: .long 0x00000001 314SCR_L_PALL: .long 0x00000002 315SCR_L_CKE_EN: .long 0x00000003 316SCR_L_CBR: .long 0x00000004 317 318STR_L_D: .long 0x000F3980 319SDR_L_D: .long 0x00000400 320EMRS_D: .long 0x00000000 321MRS1_D: .long 0x00000000 322MRS2_D: .long 0x00000000 323 324/* USB */ 325USB_USBHSC_A: .long 0xFFEC80F0 326USB_USBHSC_D: .long 0x00000000 327