1/* 2 * Copyright (C) 2009 Renesas Solutions Corp. 3 * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 4 * 5 * board/espt/lowlevel_init.S 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23#include <config.h> 24#include <version.h> 25#include <asm/processor.h> 26#include <asm/macro.h> 27 28 .global lowlevel_init 29 30 .text 31 .align 2 32 33lowlevel_init: 34 35 write32 WDTCSR_A, WDTCSR_D 36 37 write32 WDTST_A, WDTST_D 38 39 write32 WDTBST_A, WDTBST_D 40 41 write32 CCR_A, CCR_CACHE_ICI_D 42 43 write32 MMUCR_A, MMU_CONTROL_TI_D 44 45 write32 MSTPCR0_A, MSTPCR0_D 46 47 write32 MSTPCR1_A, MSTPCR1_D 48 49 write32 RAMCR_A, RAMCR_D 50 51 /* 52 * Setting infomation from 53 * original ESPT-GIGA bootloader register 54 */ 55 write32 MMSEL_A, MMSEL_D 56 57 /* dummy */ 58 mov.l @r1, r2 59 mov.l @r1, r2 60 synco 61 62 write32 BCR_A, BCR_D 63 64 write32 CS0BCR_A, CS0BCR_D 65 66 write32 CS0WCR_A, CS0WCR_D 67 68 /* 69 * DDR-SDRAM setting 70 */ 71 72 /* set DDR-SDRAM dummy read */ 73 write32 MMSEL_A, MMSEL_D 74 75 mov.l MMSEL_A, r0 76 synco 77 mov.l @r0, r1 78 synco 79 80 mov.l CS0_A, r0 81 synco 82 mov.l @r0, r1 83 synco 84 85 /* set DDR-SDRAM bus/endian etc */ 86 write32 MIM_U_A, MIM_U_D 87 88 write32 MIM_L_A, MIM_L_D0 89 90 write32 SDR_L_A, SDR_L_A_D0 91 92 write32 STR_L_A, STR_L_A_D0 93 94 /* DDR-SDRAM access control */ 95 write32 MIM_L_A, MIM_L_D1 96 97 write32 SCR_L_A, SCR_L_A_D0 98 99 write32 SCR_L_A, SCR_L_A_D1 100 101 write32 EMRS_A, EMRS_D 102 103 write32 MRS1_A, MRS1_D 104 105 write32 MIM_U_A, MIM_U_D 106 107 write32 MIM_L_A, MIM_L_A_D2 108 109 write32 SCR_L_A, SCR_L_A_D2 110 111 write32 SCR_L_A, SCR_L_A_D2 112 113 write32 MRS2_A, MRS2_D 114 115 /* wait 200us */ 116 wait_timer REPEAT_R3 117 118 /* GPIO setting */ 119 write16 PSEL0_A, PSEL0_D 120 121 write16 PSEL1_A, PSEL1_D 122 123 write16 PSEL2_A, PSEL2_D 124 125 write16 PSEL3_A, PSEL3_D 126 127 write16 PSEL4_A, PSEL4_D 128 129 write8 PADR_A, PADR_D 130 131 write16 PACR_A, PACR_D 132 133 write8 PBDR_A, PBDR_D 134 135 write16 PBCR_A, PBCR_D 136 137 write8 PCDR_A, PCDR_D 138 139 write16 PCCR_A, PCCR_D 140 141 write8 PDDR_A, PDDR_D 142 143 write16 PDCR_A, PDCR_D 144 145 write16 PECR_A, PECR_D 146 147 write16 PFCR_A, PFCR_D 148 149 write16 PGCR_A, PGCR_D 150 151 write16 PHCR_A, PHCR_D 152 153 write16 PICR_A, PICR_D 154 155 write8 PJDR_A, PJDR_D 156 157 write16 PJCR_A, PJCR_D 158 159 /* wait 50us */ 160 wait_timer REPEAT_R3 161 162 write8 PKDR_A, PKDR_D 163 164 write16 PKCR_A, PKCR_D 165 166 write16 PLCR_A, PLCR_D 167 168 write16 PMCR_A, PMCR_D 169 170 write16 PNCR_A, PNCR_D 171 172 write16 POCR_A, POCR_D 173 174 175 /* ICR0 ,ICR1 */ 176 write32 ICR0_A, ICR0_D 177 178 write32 ICR1_A, ICR1_D 179 180 /* USB Host */ 181 write32 USB_USBHSC_A, USB_USBHSC_D 182 183 write32 CCR_A, CCR_CACHE_D_2 184 185 rts 186 nop 187 188 .align 2 189 190/* GPIO Crontrol Register */ 191PACR_A: .long 0xFFEF0000 192PBCR_A: .long 0xFFEF0002 193PCCR_A: .long 0xFFEF0004 194PDCR_A: .long 0xFFEF0006 195PECR_A: .long 0xFFEF0008 196PFCR_A: .long 0xFFEF000A 197PGCR_A: .long 0xFFEF000C 198PHCR_A: .long 0xFFEF000E 199PICR_A: .long 0xFFEF0010 200PJCR_A: .long 0xFFEF0012 201PKCR_A: .long 0xFFEF0014 202PLCR_A: .long 0xFFEF0016 203PMCR_A: .long 0xFFEF0018 204PNCR_A: .long 0xFFEF001A 205POCR_A: .long 0xFFEF001C 206 207/* GPIO Data Register */ 208PADR_A: .long 0xFFEF0020 209PBDR_A: .long 0xFFEF0022 210PCDR_A: .long 0xFFEF0024 211PDDR_A: .long 0xFFEF0026 212PJDR_A: .long 0xFFEF0032 213PKDR_A: .long 0xFFEF0034 214 215/* GPIO Set data */ 216PADR_D: .long 0x00000000 217PACR_D: .long 0x00001400 218PBDR_D: .long 0x00000000 219PBCR_D: .long 0x0000555A 220PCDR_D: .long 0x00000000 221PCCR_D: .long 0x00005555 222PDDR_D: .long 0x00000000 223PDCR_D: .long 0x00000155 224PECR_D: .long 0x00000000 225PFCR_D: .long 0x00000000 226PGCR_D: .long 0x00000000 227PHCR_D: .long 0x00000000 228PICR_D: .long 0x00000800 229PJDR_D: .long 0x00000006 230PJCR_D: .long 0x00005A57 231PKDR_D: .long 0x00000000 232PKCR_D: .long 0x0000FFF9 233PLCR_D: .long 0x0000C330 234PMCR_D: .long 0x0000FFFF 235PNCR_D: .long 0x00000242 236POCR_D: .long 0x00000000 237 238/* Pin Select */ 239PSEL0_A: .long 0xFFEF0070 240PSEL1_A: .long 0xFFEF0072 241PSEL2_A: .long 0xFFEF0074 242PSEL3_A: .long 0xFFEF0076 243PSEL4_A: .long 0xFFEF0078 244PSEL0_D: .long 0x0001 245PSEL1_D: .long 0x2400 246PSEL2_D: .long 0x0000 247PSEL3_D: .long 0x2421 248PSEL4_D: .long 0x0000 249 250MMSEL_A: .long 0xFE600020 251BCR_A: .long 0xFF801000 252CS0BCR_A: .long 0xFF802000 253CS0WCR_A: .long 0xFF802008 254ICR0_A: .long 0xFFD00000 255ICR1_A: .long 0xFFD0001C 256 257MMSEL_D: .long 0xA5A50000 258BCR_D: .long 0x05000000 259CS0BCR_D: .long 0x232306F0 260CS0WCR_D: .long 0x00011104 261ICR0_D: .long 0x80C00000 262ICR1_D: .long 0x00020000 263 264/* RWBT Address */ 265WDTST_A: .long 0xFFCC0000 266WDTCSR_A: .long 0xFFCC0004 267WDTBST_A: .long 0xFFCC0008 268/* RWBT Data */ 269WDTST_D: .long 0x5A000FFF 270WDTCSR_D: .long 0xA5000000 271WDTBST_D: .long 0x55000000 272 273/* Cache Address */ 274CCR_A: .long 0xFF00001C 275MMUCR_A: .long 0xFF000010 276RAMCR_A: .long 0xFF000074 277 278/* Cache Data */ 279CCR_CACHE_ICI_D:.long 0x00000800 280CCR_CACHE_D_2: .long 0x00000103 281MMU_CONTROL_TI_D:.long 0x00000004 282RAMCR_D: .long 0x00000200 283 284/* Low power mode control Address */ 285MSTPCR0_A: .long 0xFFC80030 286MSTPCR1_A: .long 0xFFC80038 287/* Low power mode control Data */ 288MSTPCR0_D: .long 0x00000000 289MSTPCR1_D: .long 0x00000000 290 291REPEAT0_R3: .long 0x00002000 292REPEAT_R3: .long 0x00000200 293CS0_A: .long 0xA8000000 294 295MIM_U_A: .long 0xFE800008 296MIM_L_A: .long 0xFE80000C 297SCR_U_A: .long 0xFE800010 298SCR_L_A: .long 0xFE800014 299STR_U_A: .long 0xFE800018 300STR_L_A: .long 0xFE80001C 301SDR_U_A: .long 0xFE800030 302SDR_L_A: .long 0xFE800034 303EMRS_A: .long 0xFE902000 304MRS1_A: .long 0xFE900B08 305MRS2_A: .long 0xFE900308 306 307MIM_U_D: .long 0x00000000 308MIM_L_D0: .long 0x04100008 309MIM_L_D1: .long 0x02EE0009 310MIM_L_D2: .long 0x02EE0209 311 312SDR_L_A_D0: .long 0x00000300 313STR_L_A_D0: .long 0x00010040 314MIM_L_A_D1: .long 0x04100009 315SCR_L_A_D0: .long 0x00000003 316SCR_L_A_D1: .long 0x00000002 317MIM_L_A_D2: .long 0x04100209 318SCR_L_A_D2: .long 0x00000004 319 320SCR_L_NORMAL: .long 0x00000000 321SCR_L_NOP: .long 0x00000001 322SCR_L_PALL: .long 0x00000002 323SCR_L_CKE_EN: .long 0x00000003 324SCR_L_CBR: .long 0x00000004 325 326STR_L_D: .long 0x000F3980 327SDR_L_D: .long 0x00000400 328EMRS_D: .long 0x00000000 329MRS1_D: .long 0x00000000 330MRS2_D: .long 0x00000000 331 332/* USB */ 333USB_USBHSC_A: .long 0xFFEC80F0 334USB_USBHSC_D: .long 0x00000000 335