1 /* 2 * vme8349.c -- esd VME8349 board support 3 * 4 * Copyright (c) 2008-2009 esd gmbh. 5 * 6 * (C) Copyright 2006 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * Reinhard Arlt <reinhard.arlt@esd-electronics.com> 10 * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.) 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 * 30 */ 31 32 #include <common.h> 33 #include <ioports.h> 34 #include <mpc83xx.h> 35 #include <asm/mpc8349_pci.h> 36 #if defined(CONFIG_OF_LIBFDT) 37 #include <libfdt.h> 38 #endif 39 #include <asm/io.h> 40 #include <asm/mmu.h> 41 42 void ddr_enable_ecc(unsigned int dram_size); 43 44 int fixed_sdram(void) 45 { 46 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 47 u32 msize = 0; 48 u32 ddr_size; 49 u32 ddr_size_log2; 50 51 msize = CONFIG_SYS_DDR_SIZE; 52 for (ddr_size = msize << 20, ddr_size_log2 = 0; 53 (ddr_size > 1); 54 ddr_size = ddr_size>>1, ddr_size_log2++) { 55 if (ddr_size & 1) 56 return -1; 57 } 58 59 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; 60 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & 61 LAWAR_SIZE); 62 63 #if (CONFIG_SYS_DDR_SIZE == 512) 64 im->ddr.csbnds[0].csbnds = 0x0000001f; 65 #else 66 #warning Currently any DDR size other than 512MiB is not supported 67 #endif 68 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG | 0x00330000; 69 70 /* currently we use only one CS, so disable the other banks */ 71 im->ddr.csbnds[1].csbnds = 0x00000000; 72 im->ddr.csbnds[2].csbnds = 0x00000000; 73 im->ddr.csbnds[3].csbnds = 0x00000000; 74 im->ddr.cs_config[1] = 0; 75 im->ddr.cs_config[2] = 0; 76 im->ddr.cs_config[3] = 0; 77 78 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 79 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 80 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 81 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; 82 83 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; 84 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; 85 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; 86 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; 87 88 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; 89 sync(); 90 udelay(200); 91 92 /* enable DDR controller */ 93 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; 94 95 return msize; 96 } 97 98 phys_size_t initdram(int board_type) 99 { 100 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 101 u32 msize = 0; 102 103 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) 104 return -1; 105 106 /* DDR SDRAM - Main SODIMM */ 107 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; 108 109 msize = fixed_sdram(); 110 111 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 112 /* 113 * Initialize and enable DDR ECC. 114 */ 115 ddr_enable_ecc(msize * 1024 * 1024); 116 #endif 117 118 /* Now check memory size (after ECC is initialized) */ 119 msize = get_ram_size(0, msize); 120 121 /* return total bus SDRAM size(bytes) -- DDR */ 122 return msize * 1024 * 1024; 123 } 124 125 int checkboard(void) 126 { 127 puts("Board: esd VME8349\n"); 128 129 return 0; 130 } 131 132 #if defined(CONFIG_OF_BOARD_SETUP) 133 void ft_board_setup(void *blob, bd_t *bd) 134 { 135 ft_cpu_setup(blob, bd); 136 #ifdef CONFIG_PCI 137 ft_pci_setup(blob, bd); 138 #endif 139 } 140 #endif 141