1 /* 2 * vme8349.c -- esd VME8349 board support 3 * 4 * Copyright (c) 2008-2009 esd gmbh. 5 * 6 * (C) Copyright 2006 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * Reinhard Arlt <reinhard.arlt@esd-electronics.com> 10 * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.) 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <common.h> 16 #include <ioports.h> 17 #include <mpc83xx.h> 18 #include <asm/mpc8349_pci.h> 19 #if defined(CONFIG_OF_LIBFDT) 20 #include <libfdt.h> 21 #endif 22 #include <asm/io.h> 23 #include <asm/mmu.h> 24 #include <spd.h> 25 #include <spd_sdram.h> 26 #include <i2c.h> 27 #include <netdev.h> 28 29 void ddr_enable_ecc(unsigned int dram_size); 30 31 phys_size_t initdram(int board_type) 32 { 33 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 34 u32 msize = 0; 35 36 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) 37 return -1; 38 39 /* DDR SDRAM - Main memory */ 40 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; 41 42 msize = spd_sdram(); 43 44 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 45 /* 46 * Initialize and enable DDR ECC. 47 */ 48 ddr_enable_ecc(msize * 1024 * 1024); 49 #endif 50 51 /* Now check memory size (after ECC is initialized) */ 52 msize = get_ram_size(0, msize); 53 54 /* return total bus SDRAM size(bytes) -- DDR */ 55 return msize * 1024 * 1024; 56 } 57 58 int checkboard(void) 59 { 60 #ifdef VME_CADDY2 61 puts("Board: esd VME-CADDY/2\n"); 62 #else 63 puts("Board: esd VME-CPU/8349\n"); 64 #endif 65 66 return 0; 67 } 68 69 #ifdef VME_CADDY2 70 int board_eth_init(bd_t *bis) 71 { 72 return pci_eth_init(bis); 73 } 74 #endif 75 76 #if defined(CONFIG_OF_BOARD_SETUP) 77 void ft_board_setup(void *blob, bd_t *bd) 78 { 79 ft_cpu_setup(blob, bd); 80 81 #ifdef CONFIG_PCI 82 ft_pci_setup(blob, bd); 83 #endif 84 } 85 #endif 86 87 int misc_init_r() 88 { 89 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 90 91 clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0); 92 93 return 0; 94 } 95 96 /* 97 * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2 98 * and VME-CADDY/2) have different SDRAM configurations. 99 */ 100 #ifdef VME_CADDY2 101 #define SMALL_RAM 0xff 102 #define LARGE_RAM 0x00 103 #else 104 #define SMALL_RAM 0x00 105 #define LARGE_RAM 0xff 106 #endif 107 108 #define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM)) 109 110 static spd_eeprom_t default_spd_eeprom = { 111 SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */ 112 SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */ 113 SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */ 114 SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */ 115 SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */ 116 SPD_VAL(0x00, 0x00), /* 05 */ 117 SPD_VAL(0x40, 0x40), /* 06 */ 118 SPD_VAL(0x00, 0x00), /* 07 */ 119 SPD_VAL(0x05, 0x05), /* 08 */ 120 SPD_VAL(0x30, 0x30), /* 09 */ 121 SPD_VAL(0x45, 0x45), /* 10 */ 122 SPD_VAL(0x02, 0x02), /* 11 ecc used */ 123 SPD_VAL(0x82, 0x82), /* 12 */ 124 SPD_VAL(0x10, 0x10), /* 13 */ 125 SPD_VAL(0x08, 0x08), /* 14 */ 126 SPD_VAL(0x00, 0x00), /* 15 */ 127 SPD_VAL(0x0c, 0x0c), /* 16 */ 128 SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */ 129 SPD_VAL(0x38, 0x38), /* 18 */ 130 SPD_VAL(0x00, 0x00), /* 19 */ 131 SPD_VAL(0x02, 0x02), /* 20 */ 132 SPD_VAL(0x00, 0x00), /* 21 */ 133 SPD_VAL(0x03, 0x03), /* 22 */ 134 SPD_VAL(0x3d, 0x3d), /* 23 */ 135 SPD_VAL(0x45, 0x45), /* 24 */ 136 SPD_VAL(0x50, 0x50), /* 25 */ 137 SPD_VAL(0x45, 0x45), /* 26 */ 138 SPD_VAL(0x3c, 0x3c), /* 27 */ 139 SPD_VAL(0x28, 0x28), /* 28 */ 140 SPD_VAL(0x3c, 0x3c), /* 29 */ 141 SPD_VAL(0x2d, 0x2d), /* 30 */ 142 SPD_VAL(0x20, 0x80), /* 31 */ 143 SPD_VAL(0x20, 0x20), /* 32 */ 144 SPD_VAL(0x27, 0x27), /* 33 */ 145 SPD_VAL(0x10, 0x10), /* 34 */ 146 SPD_VAL(0x17, 0x17), /* 35 */ 147 SPD_VAL(0x3c, 0x3c), /* 36 */ 148 SPD_VAL(0x1e, 0x1e), /* 37 */ 149 SPD_VAL(0x1e, 0x1e), /* 38 */ 150 SPD_VAL(0x00, 0x00), /* 39 */ 151 SPD_VAL(0x00, 0x06), /* 40 */ 152 SPD_VAL(0x37, 0x37), /* 41 */ 153 SPD_VAL(0x4b, 0x7f), /* 42 */ 154 SPD_VAL(0x80, 0x80), /* 43 */ 155 SPD_VAL(0x18, 0x18), /* 44 */ 156 SPD_VAL(0x22, 0x22), /* 45 */ 157 SPD_VAL(0x00, 0x00), /* 46 */ 158 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 159 SPD_VAL(0x10, 0x10), /* 62 */ 160 SPD_VAL(0x7e, 0x1d), /* 63 */ 161 { 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' }, 162 SPD_VAL(0x00, 0x00), /* 72 */ 163 #ifdef VME_CADDY2 164 { "vme-caddy/2 ram " } 165 #else 166 { "vme-cpu/2 ram " } 167 #endif 168 }; 169 170 int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len) 171 { 172 int old_bus = i2c_get_bus_num(); 173 unsigned int l, sum; 174 int valid = 0; 175 176 i2c_set_bus_num(0); 177 178 if (i2c_read(chip, addr, alen, buffer, len) == 0) 179 if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) { 180 sum = 0; 181 for (l = 0; l < 63; l++) 182 sum = (sum + buffer[l]) & 0xff; 183 if (sum == buffer[63]) 184 valid = 1; 185 else 186 printf("Invalid checksum in EEPROM %02x %02x\n", 187 sum, buffer[63]); 188 } 189 190 if (valid == 0) { 191 memcpy(buffer, (void *)&default_spd_eeprom, len); 192 sum = 0; 193 for (l = 0; l < 63; l++) 194 sum = (sum + buffer[l]) & 0xff; 195 if (sum != buffer[63]) 196 printf("Invalid checksum in FLASH %02x %02x\n", 197 sum, buffer[63]); 198 buffer[63] = sum; 199 } 200 201 i2c_set_bus_num(old_bus); 202 203 return 0; 204 } 205