1 /* 2 * pci.c -- esd VME8349 PCI board support. 3 * Copyright (c) 2006 Wind River Systems, Inc. 4 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. 5 * Copyright (c) 2009 esd gmbh. 6 * 7 * Reinhard Arlt <reinhard.arlt@esd-electronics.com> 8 * 9 * Based on MPC8349 PCI support but w/o PIB related code. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <asm/mmu.h> 15 #include <asm/io.h> 16 #include <common.h> 17 #include <mpc83xx.h> 18 #include <pci.h> 19 #include <i2c.h> 20 #include <asm/fsl_i2c.h> 21 #include "vme8349pin.h" 22 23 static struct pci_region pci1_regions[] = { 24 { 25 bus_start: CONFIG_SYS_PCI1_MEM_BASE, 26 phys_start: CONFIG_SYS_PCI1_MEM_PHYS, 27 size: CONFIG_SYS_PCI1_MEM_SIZE, 28 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 29 }, 30 { 31 bus_start: CONFIG_SYS_PCI1_IO_BASE, 32 phys_start: CONFIG_SYS_PCI1_IO_PHYS, 33 size: CONFIG_SYS_PCI1_IO_SIZE, 34 flags: PCI_REGION_IO 35 }, 36 { 37 bus_start: CONFIG_SYS_PCI1_MMIO_BASE, 38 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, 39 size: CONFIG_SYS_PCI1_MMIO_SIZE, 40 flags: PCI_REGION_MEM 41 }, 42 }; 43 44 /* 45 * pci_init_board() 46 * 47 * NOTICE: PCI2 is not supported. There is only one 48 * physical PCI slot on the board. 49 * 50 */ 51 void 52 pci_init_board(void) 53 { 54 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; 55 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; 56 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; 57 struct pci_region *reg[] = { pci1_regions }; 58 u8 reg8; 59 int monarch = 0; 60 61 i2c_set_bus_num(1); 62 /* Read the PCI_M66EN jumper setting */ 63 if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, 1) == 0) || 64 (i2c_read(0x38 , 0, 0, ®8, 1) == 0)) { 65 if (reg8 & 0x40) { 66 clk->occr = 0xff000000; /* 66 MHz PCI */ 67 printf("PCI: 66MHz\n"); 68 } else { 69 clk->occr = 0xffff0003; /* 33 MHz PCI */ 70 printf("PCI: 33MHz\n"); 71 } 72 if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0)) 73 monarch = 1; 74 } else { 75 clk->occr = 0xffff0003; /* 33 MHz PCI */ 76 printf("PCI: 33MHz (I2C read failed)\n"); 77 } 78 udelay(2000); 79 80 /* 81 * Assert/deassert VME reset 82 */ 83 clrsetbits_be32(&immr->gpio[1].dat, 84 GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N, 85 GPIO2_VME_RESET_N | GPIO2_L_RESET_EN_N); 86 setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N | 87 GPIO2_TSI_POWERUP_RESET_N | 88 GPIO2_VME_RESET_N | 89 GPIO2_L_RESET_EN_N); 90 clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON); 91 udelay(200); 92 setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N); 93 udelay(200); 94 setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N); 95 udelay(600000); 96 clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N); 97 98 /* Configure PCI Local Access Windows */ 99 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; 100 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; 101 102 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; 103 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; 104 105 udelay(2000); 106 107 if (monarch == 0) { 108 mpc83xx_pci_init(1, reg); 109 } else { 110 /* 111 * Release PCI RST Output signal 112 */ 113 out_be32(&immr->pci_ctrl[0].gcr, 0); 114 udelay(2000); 115 out_be32(&immr->pci_ctrl[0].gcr, 1); 116 } 117 } 118