1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2007-2008 4 * Stelian Pop <stelian@popies.net> 5 * Lead Tech Design <www.leadtechdesign.com> 6 * 7 * (C) Copyright 2009-2015 8 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> 9 * esd electronic system design gmbh <www.esd.eu> 10 */ 11 12 #include <common.h> 13 #include <asm/io.h> 14 #include <asm/gpio.h> 15 #include <asm/mach-types.h> 16 #include <asm/setup.h> 17 #include <asm/arch/at91sam9_smc.h> 18 #include <asm/arch/at91_common.h> 19 #include <asm/arch/at91_pmc.h> 20 #include <asm/arch/at91_rstc.h> 21 #include <asm/arch/at91_matrix.h> 22 #include <asm/arch/at91_pio.h> 23 #include <asm/arch/clk.h> 24 #include <netdev.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 /* 29 * Miscelaneous platform dependent initialisations 30 */ 31 32 #ifdef CONFIG_REVISION_TAG 33 static int hw_rev = -1; /* hardware revision */ 34 35 int get_hw_rev(void) 36 { 37 if (hw_rev >= 0) 38 return hw_rev; 39 40 hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19); 41 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1; 42 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2; 43 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3; 44 45 if (hw_rev == 15) 46 hw_rev = 0; 47 48 return hw_rev; 49 } 50 #endif /* CONFIG_REVISION_TAG */ 51 52 #ifdef CONFIG_CMD_NAND 53 static void meesc_nand_hw_init(void) 54 { 55 unsigned long csa; 56 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; 57 at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; 58 59 /* Enable CS3 */ 60 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; 61 writel(csa, &matrix->csa[0]); 62 63 /* Configure SMC CS3 for NAND/SmartMedia */ 64 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 65 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2), 66 &smc->cs[3].setup); 67 68 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 69 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 70 &smc->cs[3].pulse); 71 72 writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6), 73 &smc->cs[3].cycle); 74 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 75 AT91_SMC_MODE_EXNW_DISABLE | 76 AT91_SMC_MODE_DBW_8 | 77 AT91_SMC_MODE_TDF_CYCLE(12), 78 &smc->cs[3].mode); 79 80 /* Configure RDY/BSY */ 81 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); 82 83 /* Enable NandFlash */ 84 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 85 } 86 #endif /* CONFIG_CMD_NAND */ 87 88 #ifdef CONFIG_MACB 89 static void meesc_macb_hw_init(void) 90 { 91 at91_periph_clk_enable(ATMEL_ID_EMAC); 92 93 at91_macb_hw_init(); 94 } 95 #endif 96 97 /* 98 * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT 99 * controller debugging 100 * The ET1100 is located at physical address 0x70000000 101 * Its process memory is located at physical address 0x70001000 102 */ 103 static void meesc_ethercat_hw_init(void) 104 { 105 at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1; 106 107 /* Configure SMC EBI1_CS0 for EtherCAT */ 108 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | 109 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0), 110 &smc1->cs[0].setup); 111 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) | 112 AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9), 113 &smc1->cs[0].pulse); 114 writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6), 115 &smc1->cs[0].cycle); 116 /* 117 * Configure behavior at external wait signal, byte-select mode, 16 bit 118 * data bus width, none data float wait states and TDF optimization 119 */ 120 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY | 121 AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) | 122 AT91_SMC_MODE_TDF, &smc1->cs[0].mode); 123 124 /* Configure RDY/BSY */ 125 at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */ 126 } 127 128 int dram_init(void) 129 { 130 /* dram_init must store complete ramsize in gd->ram_size */ 131 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, 132 PHYS_SDRAM_SIZE); 133 return 0; 134 } 135 136 int dram_init_banksize(void) 137 { 138 gd->bd->bi_dram[0].start = PHYS_SDRAM; 139 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 140 141 return 0; 142 } 143 144 int board_eth_init(bd_t *bis) 145 { 146 int rc = 0; 147 #ifdef CONFIG_MACB 148 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); 149 #endif 150 return rc; 151 } 152 153 #ifdef CONFIG_DISPLAY_BOARDINFO 154 int checkboard(void) 155 { 156 char str[32]; 157 u_char hw_type; /* hardware type */ 158 159 /* read the "Type" register of the ET1100 controller */ 160 hw_type = readb(CONFIG_ET1100_BASE); 161 162 switch (hw_type) { 163 case 0x11: 164 case 0x3F: 165 /* ET1100 present, arch number of MEESC-Board */ 166 gd->bd->bi_arch_number = MACH_TYPE_MEESC; 167 puts("Board: CAN-EtherCAT Gateway"); 168 break; 169 case 0xFF: 170 /* no ET1100 present, arch number of EtherCAN/2-Board */ 171 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2; 172 puts("Board: EtherCAN/2 Gateway"); 173 /* switch on LED1D */ 174 at91_set_pio_output(AT91_PIO_PORTB, 12, 1); 175 break; 176 default: 177 /* assume, no ET1100 present, arch number of EtherCAN/2-Board */ 178 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2; 179 printf("ERROR! Read invalid hw_type: %02X\n", hw_type); 180 puts("Board: EtherCAN/2 Gateway"); 181 break; 182 } 183 if (env_get_f("serial#", str, sizeof(str)) > 0) { 184 puts(", serial# "); 185 puts(str); 186 } 187 #ifdef CONFIG_REVISION_TAG 188 printf("\nHardware-revision: 1.%d\n", get_hw_rev()); 189 #endif 190 printf("Mach-type: %lu\n", gd->bd->bi_arch_number); 191 return 0; 192 } 193 #endif /* CONFIG_DISPLAY_BOARDINFO */ 194 195 #ifdef CONFIG_SERIAL_TAG 196 void get_board_serial(struct tag_serialnr *serialnr) 197 { 198 char *str; 199 200 char *serial = env_get("serial#"); 201 if (serial) { 202 str = strchr(serial, '_'); 203 if (str && (strlen(str) >= 4)) { 204 serialnr->high = (*(str + 1) << 8) | *(str + 2); 205 serialnr->low = simple_strtoul(str + 3, NULL, 16); 206 } 207 } else { 208 serialnr->high = 0; 209 serialnr->low = 0; 210 } 211 } 212 #endif 213 214 #ifdef CONFIG_REVISION_TAG 215 u32 get_board_rev(void) 216 { 217 return hw_rev | 0x100; 218 } 219 #endif 220 221 #ifdef CONFIG_MISC_INIT_R 222 int misc_init_r(void) 223 { 224 char *str; 225 char buf[32]; 226 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; 227 228 /* 229 * Normally the processor clock has a divisor of 2. 230 * In some cases this this needs to be set to 4. 231 * Check the user has set environment mdiv to 4 to change the divisor. 232 */ 233 str = env_get("mdiv"); 234 if (str && (strcmp(str, "4") == 0)) { 235 writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) | 236 AT91SAM9_PMC_MDIV_4, &pmc->mckr); 237 at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); 238 serial_setbrg(); 239 /* Notify the user that the clock is not default */ 240 printf("Setting master clock to %s MHz\n", 241 strmhz(buf, get_mck_clk_rate())); 242 } 243 244 return 0; 245 } 246 #endif /* CONFIG_MISC_INIT_R */ 247 248 int board_early_init_f(void) 249 { 250 at91_periph_clk_enable(ATMEL_ID_UHP); 251 252 return 0; 253 } 254 255 int board_init(void) 256 { 257 /* initialize ET1100 Controller */ 258 meesc_ethercat_hw_init(); 259 260 /* adress of boot parameters */ 261 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 262 263 #ifdef CONFIG_CMD_NAND 264 meesc_nand_hw_init(); 265 #endif 266 #ifdef CONFIG_MACB 267 meesc_macb_hw_init(); 268 #endif 269 #ifdef CONFIG_AT91_CAN 270 at91_can_hw_init(); 271 #endif 272 #ifdef CONFIG_USB_OHCI_NEW 273 at91_uhp_hw_init(); 274 #endif 275 return 0; 276 } 277