1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * (C) Copyright 2009-2015 7 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> 8 * esd electronic system design gmbh <www.esd.eu> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <asm/io.h> 15 #include <asm/gpio.h> 16 #include <asm/arch/at91sam9_smc.h> 17 #include <asm/arch/at91_common.h> 18 #include <asm/arch/at91_pmc.h> 19 #include <asm/arch/at91_rstc.h> 20 #include <asm/arch/at91_matrix.h> 21 #include <asm/arch/at91_pio.h> 22 #include <asm/arch/clk.h> 23 #include <netdev.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 /* 28 * Miscelaneous platform dependent initialisations 29 */ 30 31 #ifdef CONFIG_REVISION_TAG 32 static int hw_rev = -1; /* hardware revision */ 33 34 int get_hw_rev(void) 35 { 36 if (hw_rev >= 0) 37 return hw_rev; 38 39 hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19); 40 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1; 41 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2; 42 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3; 43 44 if (hw_rev == 15) 45 hw_rev = 0; 46 47 return hw_rev; 48 } 49 #endif /* CONFIG_REVISION_TAG */ 50 51 #ifdef CONFIG_CMD_NAND 52 static void meesc_nand_hw_init(void) 53 { 54 unsigned long csa; 55 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; 56 at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; 57 58 /* Enable CS3 */ 59 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; 60 writel(csa, &matrix->csa[0]); 61 62 /* Configure SMC CS3 for NAND/SmartMedia */ 63 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 64 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2), 65 &smc->cs[3].setup); 66 67 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 68 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 69 &smc->cs[3].pulse); 70 71 writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6), 72 &smc->cs[3].cycle); 73 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 74 AT91_SMC_MODE_EXNW_DISABLE | 75 AT91_SMC_MODE_DBW_8 | 76 AT91_SMC_MODE_TDF_CYCLE(12), 77 &smc->cs[3].mode); 78 79 /* Configure RDY/BSY */ 80 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); 81 82 /* Enable NandFlash */ 83 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 84 } 85 #endif /* CONFIG_CMD_NAND */ 86 87 #ifdef CONFIG_MACB 88 static void meesc_macb_hw_init(void) 89 { 90 at91_periph_clk_enable(ATMEL_ID_EMAC); 91 92 at91_macb_hw_init(); 93 } 94 #endif 95 96 /* 97 * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT 98 * controller debugging 99 * The ET1100 is located at physical address 0x70000000 100 * Its process memory is located at physical address 0x70001000 101 */ 102 static void meesc_ethercat_hw_init(void) 103 { 104 at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1; 105 106 /* Configure SMC EBI1_CS0 for EtherCAT */ 107 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | 108 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0), 109 &smc1->cs[0].setup); 110 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) | 111 AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9), 112 &smc1->cs[0].pulse); 113 writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6), 114 &smc1->cs[0].cycle); 115 /* 116 * Configure behavior at external wait signal, byte-select mode, 16 bit 117 * data bus width, none data float wait states and TDF optimization 118 */ 119 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY | 120 AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) | 121 AT91_SMC_MODE_TDF, &smc1->cs[0].mode); 122 123 /* Configure RDY/BSY */ 124 at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */ 125 } 126 127 int dram_init(void) 128 { 129 /* dram_init must store complete ramsize in gd->ram_size */ 130 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, 131 PHYS_SDRAM_SIZE); 132 return 0; 133 } 134 135 void dram_init_banksize(void) 136 { 137 gd->bd->bi_dram[0].start = PHYS_SDRAM; 138 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 139 } 140 141 int board_eth_init(bd_t *bis) 142 { 143 int rc = 0; 144 #ifdef CONFIG_MACB 145 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); 146 #endif 147 return rc; 148 } 149 150 #ifdef CONFIG_DISPLAY_BOARDINFO 151 int checkboard(void) 152 { 153 char str[32]; 154 u_char hw_type; /* hardware type */ 155 156 /* read the "Type" register of the ET1100 controller */ 157 hw_type = readb(CONFIG_ET1100_BASE); 158 159 switch (hw_type) { 160 case 0x11: 161 case 0x3F: 162 /* ET1100 present, arch number of MEESC-Board */ 163 gd->bd->bi_arch_number = MACH_TYPE_MEESC; 164 puts("Board: CAN-EtherCAT Gateway"); 165 break; 166 case 0xFF: 167 /* no ET1100 present, arch number of EtherCAN/2-Board */ 168 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2; 169 puts("Board: EtherCAN/2 Gateway"); 170 /* switch on LED1D */ 171 at91_set_pio_output(AT91_PIO_PORTB, 12, 1); 172 break; 173 default: 174 /* assume, no ET1100 present, arch number of EtherCAN/2-Board */ 175 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2; 176 printf("ERROR! Read invalid hw_type: %02X\n", hw_type); 177 puts("Board: EtherCAN/2 Gateway"); 178 break; 179 } 180 if (getenv_f("serial#", str, sizeof(str)) > 0) { 181 puts(", serial# "); 182 puts(str); 183 } 184 #ifdef CONFIG_REVISION_TAG 185 printf("\nHardware-revision: 1.%d\n", get_hw_rev()); 186 #endif 187 printf("Mach-type: %lu\n", gd->bd->bi_arch_number); 188 return 0; 189 } 190 #endif /* CONFIG_DISPLAY_BOARDINFO */ 191 192 #ifdef CONFIG_SERIAL_TAG 193 void get_board_serial(struct tag_serialnr *serialnr) 194 { 195 char *str; 196 197 char *serial = getenv("serial#"); 198 if (serial) { 199 str = strchr(serial, '_'); 200 if (str && (strlen(str) >= 4)) { 201 serialnr->high = (*(str + 1) << 8) | *(str + 2); 202 serialnr->low = simple_strtoul(str + 3, NULL, 16); 203 } 204 } else { 205 serialnr->high = 0; 206 serialnr->low = 0; 207 } 208 } 209 #endif 210 211 #ifdef CONFIG_REVISION_TAG 212 u32 get_board_rev(void) 213 { 214 return hw_rev | 0x100; 215 } 216 #endif 217 218 #ifdef CONFIG_MISC_INIT_R 219 int misc_init_r(void) 220 { 221 char *str; 222 char buf[32]; 223 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; 224 225 /* 226 * Normally the processor clock has a divisor of 2. 227 * In some cases this this needs to be set to 4. 228 * Check the user has set environment mdiv to 4 to change the divisor. 229 */ 230 if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) { 231 writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) | 232 AT91SAM9_PMC_MDIV_4, &pmc->mckr); 233 at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); 234 serial_setbrg(); 235 /* Notify the user that the clock is not default */ 236 printf("Setting master clock to %s MHz\n", 237 strmhz(buf, get_mck_clk_rate())); 238 } 239 240 return 0; 241 } 242 #endif /* CONFIG_MISC_INIT_R */ 243 244 int board_early_init_f(void) 245 { 246 at91_periph_clk_enable(ATMEL_ID_PIOA); 247 at91_periph_clk_enable(ATMEL_ID_PIOB); 248 at91_periph_clk_enable(ATMEL_ID_PIOCDE); 249 at91_periph_clk_enable(ATMEL_ID_UHP); 250 251 at91_seriald_hw_init(); 252 253 return 0; 254 } 255 256 int board_init(void) 257 { 258 /* initialize ET1100 Controller */ 259 meesc_ethercat_hw_init(); 260 261 /* adress of boot parameters */ 262 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 263 264 #ifdef CONFIG_CMD_NAND 265 meesc_nand_hw_init(); 266 #endif 267 #ifdef CONFIG_HAS_DATAFLASH 268 at91_spi0_hw_init(1 << 0); 269 #endif 270 #ifdef CONFIG_MACB 271 meesc_macb_hw_init(); 272 #endif 273 #ifdef CONFIG_AT91_CAN 274 at91_can_hw_init(); 275 #endif 276 #ifdef CONFIG_USB_OHCI_NEW 277 at91_uhp_hw_init(); 278 #endif 279 return 0; 280 } 281