1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian.pop@leadtechdesign.com> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * (C) Copyright 2009-2010 7 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> 8 * esd electronic system design gmbh <www.esd.eu> 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 #include <common.h> 30 #include <asm/arch/at91sam9263.h> 31 #include <asm/arch/at91sam9_smc.h> 32 #include <asm/arch/at91_common.h> 33 #include <asm/arch/at91_pmc.h> 34 #include <asm/arch/at91_rstc.h> 35 #include <asm/arch/at91_matrix.h> 36 #include <asm/arch/at91_pio.h> 37 #include <asm/arch/clk.h> 38 #include <asm/arch/hardware.h> 39 #include <asm/arch/io.h> 40 #include <netdev.h> 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 /* 45 * Miscelaneous platform dependent initialisations 46 */ 47 48 static int hw_rev = -1; /* hardware revision */ 49 50 int get_hw_rev(void) 51 { 52 if (hw_rev >= 0) 53 return hw_rev; 54 55 hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19); 56 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1; 57 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2; 58 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3; 59 60 if (hw_rev == 15) 61 hw_rev = 0; 62 63 return hw_rev; 64 } 65 66 #ifdef CONFIG_CMD_NAND 67 static void meesc_nand_hw_init(void) 68 { 69 unsigned long csa; 70 at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE; 71 at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; 72 73 /* Enable CS3 */ 74 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; 75 writel(csa, &matrix->csa[0]); 76 77 /* Configure SMC CS3 for NAND/SmartMedia */ 78 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 79 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 80 &smc->cs[3].setup); 81 82 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 83 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 84 &smc->cs[3].pulse); 85 86 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 87 &smc->cs[3].cycle); 88 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 89 AT91_SMC_MODE_EXNW_DISABLE | 90 AT91_SMC_MODE_DBW_8 | 91 AT91_SMC_MODE_TDF_CYCLE(2), 92 &smc->cs[3].mode); 93 94 /* Configure RDY/BSY */ 95 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); 96 97 /* Enable NandFlash */ 98 at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 99 } 100 #endif /* CONFIG_CMD_NAND */ 101 102 #ifdef CONFIG_MACB 103 static void meesc_macb_hw_init(void) 104 { 105 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; 106 /* Enable clock */ 107 writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer); 108 at91_macb_hw_init(); 109 } 110 #endif 111 112 /* 113 * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT 114 * controller debugging 115 * The ET1100 is located at physical address 0x70000000 116 * Its process memory is located at physical address 0x70001000 117 */ 118 static void meesc_ethercat_hw_init(void) 119 { 120 at91_smc_t *smc1 = (at91_smc_t *) AT91_SMC1_BASE; 121 122 /* Configure SMC EBI1_CS0 for EtherCAT */ 123 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | 124 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0), 125 &smc1->cs[0].setup); 126 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) | 127 AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9), 128 &smc1->cs[0].pulse); 129 writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6), 130 &smc1->cs[0].cycle); 131 /* 132 * Configure behavior at external wait signal, byte-select mode, 16 bit 133 * data bus width, none data float wait states and TDF optimization 134 */ 135 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY | 136 AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) | 137 AT91_SMC_MODE_TDF, &smc1->cs[0].mode); 138 139 /* Configure RDY/BSY */ 140 at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */ 141 } 142 143 int dram_init(void) 144 { 145 gd->bd->bi_dram[0].start = PHYS_SDRAM; 146 gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27)); 147 return 0; 148 } 149 150 int board_eth_init(bd_t *bis) 151 { 152 int rc = 0; 153 #ifdef CONFIG_MACB 154 rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00); 155 #endif 156 return rc; 157 } 158 159 int checkboard(void) 160 { 161 char str[32]; 162 u_char hw_type; /* hardware type */ 163 164 /* read the "Type" register of the ET1100 controller */ 165 hw_type = readb(CONFIG_ET1100_BASE); 166 167 switch (hw_type) { 168 case 0x11: 169 case 0x3F: 170 /* ET1100 present, arch number of MEESC-Board */ 171 gd->bd->bi_arch_number = MACH_TYPE_MEESC; 172 puts("Board: CAN-EtherCAT Gateway"); 173 break; 174 case 0xFF: 175 /* no ET1100 present, arch number of EtherCAN/2-Board */ 176 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2; 177 puts("Board: EtherCAN/2 Gateway"); 178 /* switch on LED1D */ 179 at91_set_pio_output(AT91_PIO_PORTB, 12, 1); 180 break; 181 default: 182 /* assume, no ET1100 present, arch number of EtherCAN/2-Board */ 183 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2; 184 printf("ERROR! Read invalid hw_type: %02X\n", hw_type); 185 puts("Board: EtherCAN/2 Gateway"); 186 break; 187 } 188 if (getenv_f("serial#", str, sizeof(str)) > 0) { 189 puts(", serial# "); 190 puts(str); 191 } 192 printf("\nHardware-revision: 1.%d\n", get_hw_rev()); 193 printf("Mach-type: %lu\n", gd->bd->bi_arch_number); 194 return 0; 195 } 196 197 #ifdef CONFIG_SERIAL_TAG 198 void get_board_serial(struct tag_serialnr *serialnr) 199 { 200 char *str; 201 202 char *serial = getenv("serial#"); 203 if (serial) { 204 str = strchr(serial, '_'); 205 if (str && (strlen(str) >= 4)) { 206 serialnr->high = (*(str + 1) << 8) | *(str + 2); 207 serialnr->low = simple_strtoul(str + 3, NULL, 16); 208 } 209 } else { 210 serialnr->high = 0; 211 serialnr->low = 0; 212 } 213 } 214 #endif 215 216 #ifdef CONFIG_REVISION_TAG 217 u32 get_board_rev(void) 218 { 219 return hw_rev | 0x100; 220 } 221 #endif 222 223 #ifdef CONFIG_MISC_INIT_R 224 int misc_init_r(void) 225 { 226 char *str; 227 char buf[32]; 228 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; 229 230 /* 231 * Normally the processor clock has a divisor of 2. 232 * In some cases this this needs to be set to 4. 233 * Check the user has set environment mdiv to 4 to change the divisor. 234 */ 235 if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) { 236 writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) | 237 AT91SAM9_PMC_MDIV_4, &pmc->mckr); 238 at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); 239 serial_setbrg(); 240 /* Notify the user that the clock is not default */ 241 printf("Setting master clock to %s MHz\n", 242 strmhz(buf, get_mck_clk_rate())); 243 } 244 245 return 0; 246 } 247 #endif /* CONFIG_MISC_INIT_R */ 248 249 int board_init(void) 250 { 251 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; 252 253 /* Peripheral Clock Enable Register */ 254 writel(1 << AT91SAM9263_ID_PIOA | 255 1 << AT91SAM9263_ID_PIOB | 256 1 << AT91SAM9263_ID_PIOCDE | 257 1 << AT91SAM9263_ID_UHP, 258 &pmc->pcer); 259 260 /* initialize ET1100 Controller */ 261 meesc_ethercat_hw_init(); 262 263 /* adress of boot parameters */ 264 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 265 266 at91_serial_hw_init(); 267 #ifdef CONFIG_CMD_NAND 268 meesc_nand_hw_init(); 269 #endif 270 #ifdef CONFIG_HAS_DATAFLASH 271 at91_spi0_hw_init(1 << 0); 272 #endif 273 #ifdef CONFIG_MACB 274 meesc_macb_hw_init(); 275 #endif 276 #ifdef CONFIG_AT91_CAN 277 at91_can_hw_init(); 278 #endif 279 #ifdef CONFIG_USB_OHCI_NEW 280 at91_uhp_hw_init(); 281 #endif 282 return 0; 283 } 284