xref: /openbmc/u-boot/board/esd/meesc/meesc.c (revision 3e9aa320)
1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * (C) Copyright 2009-2011
7  * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
8  * esd electronic system design gmbh <www.esd.eu>
9  *
10  * SPDX-License-Identifier:	GPL-2.0+
11  */
12 
13 #include <common.h>
14 #include <asm/io.h>
15 #include <asm/gpio.h>
16 #include <asm/arch/at91sam9_smc.h>
17 #include <asm/arch/at91_common.h>
18 #include <asm/arch/at91_pmc.h>
19 #include <asm/arch/at91_rstc.h>
20 #include <asm/arch/at91_matrix.h>
21 #include <asm/arch/at91_pio.h>
22 #include <asm/arch/clk.h>
23 #include <netdev.h>
24 
25 DECLARE_GLOBAL_DATA_PTR;
26 
27 /*
28  * Miscelaneous platform dependent initialisations
29  */
30 
31 static int hw_rev = -1;	/* hardware revision */
32 
33 int get_hw_rev(void)
34 {
35 	if (hw_rev >= 0)
36 		return hw_rev;
37 
38 	hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
39 	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
40 	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
41 	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
42 
43 	if (hw_rev == 15)
44 		hw_rev = 0;
45 
46 	return hw_rev;
47 }
48 
49 #ifdef CONFIG_CMD_NAND
50 static void meesc_nand_hw_init(void)
51 {
52 	unsigned long csa;
53 	at91_smc_t	*smc	= (at91_smc_t *) ATMEL_BASE_SMC0;
54 	at91_matrix_t	*matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
55 
56 	/* Enable CS3 */
57 	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
58 	writel(csa, &matrix->csa[0]);
59 
60 	/* Configure SMC CS3 for NAND/SmartMedia */
61 	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
62 		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
63 		&smc->cs[3].setup);
64 
65 	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
66 		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
67 		&smc->cs[3].pulse);
68 
69 	writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
70 		&smc->cs[3].cycle);
71 	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
72 		AT91_SMC_MODE_EXNW_DISABLE |
73 		AT91_SMC_MODE_DBW_8 |
74 		AT91_SMC_MODE_TDF_CYCLE(12),
75 		&smc->cs[3].mode);
76 
77 	/* Configure RDY/BSY */
78 	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
79 
80 	/* Enable NandFlash */
81 	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
82 }
83 #endif /* CONFIG_CMD_NAND */
84 
85 #ifdef CONFIG_MACB
86 static void meesc_macb_hw_init(void)
87 {
88 	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
89 	/* Enable clock */
90 	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
91 	at91_macb_hw_init();
92 }
93 #endif
94 
95 /*
96  * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
97  * controller debugging
98  * The ET1100 is located at physical address 0x70000000
99  * Its process memory is located at physical address 0x70001000
100  */
101 static void meesc_ethercat_hw_init(void)
102 {
103 	at91_smc_t	*smc1	= (at91_smc_t *) ATMEL_BASE_SMC1;
104 
105 	/* Configure SMC EBI1_CS0 for EtherCAT */
106 	writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
107 		AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
108 		&smc1->cs[0].setup);
109 	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
110 		AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
111 		&smc1->cs[0].pulse);
112 	writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
113 		&smc1->cs[0].cycle);
114 	/*
115 	 * Configure behavior at external wait signal, byte-select mode, 16 bit
116 	 * data bus width, none data float wait states and TDF optimization
117 	 */
118 	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
119 		AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
120 		AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
121 
122 	/* Configure RDY/BSY */
123 	at91_set_b_periph(AT91_PIO_PORTE, 20, 0);	/* EBI1_NWAIT */
124 }
125 
126 int dram_init(void)
127 {
128 	gd->ram_size = get_ram_size(
129 		(void *)CONFIG_SYS_SDRAM_BASE,
130 		CONFIG_SYS_SDRAM_SIZE);
131 	return 0;
132 }
133 
134 int board_eth_init(bd_t *bis)
135 {
136 	int rc = 0;
137 #ifdef CONFIG_MACB
138 	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
139 #endif
140 	return rc;
141 }
142 
143 int checkboard(void)
144 {
145 	char str[32];
146 	u_char hw_type;	/* hardware type */
147 
148 	/* read the "Type" register of the ET1100 controller */
149 	hw_type = readb(CONFIG_ET1100_BASE);
150 
151 	switch (hw_type) {
152 	case 0x11:
153 	case 0x3F:
154 		/* ET1100 present, arch number of MEESC-Board */
155 		gd->bd->bi_arch_number = MACH_TYPE_MEESC;
156 		puts("Board: CAN-EtherCAT Gateway");
157 		break;
158 	case 0xFF:
159 		/* no ET1100 present, arch number of EtherCAN/2-Board */
160 		gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
161 		puts("Board: EtherCAN/2 Gateway");
162 		/* switch on LED1D */
163 		at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
164 		break;
165 	default:
166 		/* assume, no ET1100 present, arch number of EtherCAN/2-Board */
167 		gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
168 		printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
169 		puts("Board: EtherCAN/2 Gateway");
170 		break;
171 	}
172 	if (getenv_f("serial#", str, sizeof(str)) > 0) {
173 		puts(", serial# ");
174 		puts(str);
175 	}
176 	printf("\nHardware-revision: 1.%d\n", get_hw_rev());
177 	printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
178 	return 0;
179 }
180 
181 #ifdef CONFIG_SERIAL_TAG
182 void get_board_serial(struct tag_serialnr *serialnr)
183 {
184 	char *str;
185 
186 	char *serial = getenv("serial#");
187 	if (serial) {
188 		str = strchr(serial, '_');
189 		if (str && (strlen(str) >= 4)) {
190 			serialnr->high = (*(str + 1) << 8) | *(str + 2);
191 			serialnr->low = simple_strtoul(str + 3, NULL, 16);
192 		}
193 	} else {
194 		serialnr->high = 0;
195 		serialnr->low = 0;
196 	}
197 }
198 #endif
199 
200 #ifdef CONFIG_REVISION_TAG
201 u32 get_board_rev(void)
202 {
203 	return hw_rev | 0x100;
204 }
205 #endif
206 
207 #ifdef CONFIG_MISC_INIT_R
208 int misc_init_r(void)
209 {
210 	char		*str;
211 	char		buf[32];
212 	at91_pmc_t	*pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
213 
214 	/*
215 	 * Normally the processor clock has a divisor of 2.
216 	 * In some cases this this needs to be set to 4.
217 	 * Check the user has set environment mdiv to 4 to change the divisor.
218 	 */
219 	if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
220 		writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
221 			AT91SAM9_PMC_MDIV_4, &pmc->mckr);
222 		at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
223 		serial_setbrg();
224 		/* Notify the user that the clock is not default */
225 		printf("Setting master clock to %s MHz\n",
226 			strmhz(buf, get_mck_clk_rate()));
227 	}
228 
229 	return 0;
230 }
231 #endif /* CONFIG_MISC_INIT_R */
232 
233 int board_early_init_f(void)
234 {
235 	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
236 
237 	/* enable all clocks */
238 	writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
239 		(1 << ATMEL_ID_PIOCDE) | (1 << ATMEL_ID_UHP),
240 		&pmc->pcer);
241 
242 	at91_seriald_hw_init();
243 
244 	return 0;
245 }
246 
247 int board_init(void)
248 {
249 	/* initialize ET1100 Controller */
250 	meesc_ethercat_hw_init();
251 
252 	/* adress of boot parameters */
253 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
254 
255 #ifdef CONFIG_CMD_NAND
256 	meesc_nand_hw_init();
257 #endif
258 #ifdef CONFIG_HAS_DATAFLASH
259 	at91_spi0_hw_init(1 << 0);
260 #endif
261 #ifdef CONFIG_MACB
262 	meesc_macb_hw_init();
263 #endif
264 #ifdef CONFIG_AT91_CAN
265 	at91_can_hw_init();
266 #endif
267 #ifdef CONFIG_USB_OHCI_NEW
268 	at91_uhp_hw_init();
269 #endif
270 	return 0;
271 }
272