1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * (C) Copyright 2009-2015 7 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> 8 * esd electronic system design gmbh <www.esd.eu> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <asm/io.h> 15 #include <asm/gpio.h> 16 #include <asm/arch/at91sam9_smc.h> 17 #include <asm/arch/at91_common.h> 18 #include <asm/arch/at91_pmc.h> 19 #include <asm/arch/at91_rstc.h> 20 #include <asm/arch/at91_matrix.h> 21 #include <asm/arch/at91_pio.h> 22 #include <asm/arch/clk.h> 23 #include <netdev.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 /* 28 * Miscelaneous platform dependent initialisations 29 */ 30 31 #ifdef CONFIG_REVISION_TAG 32 static int hw_rev = -1; /* hardware revision */ 33 34 int get_hw_rev(void) 35 { 36 if (hw_rev >= 0) 37 return hw_rev; 38 39 hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19); 40 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1; 41 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2; 42 hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3; 43 44 if (hw_rev == 15) 45 hw_rev = 0; 46 47 return hw_rev; 48 } 49 #endif /* CONFIG_REVISION_TAG */ 50 51 #ifdef CONFIG_CMD_NAND 52 static void meesc_nand_hw_init(void) 53 { 54 unsigned long csa; 55 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; 56 at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; 57 58 /* Enable CS3 */ 59 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; 60 writel(csa, &matrix->csa[0]); 61 62 /* Configure SMC CS3 for NAND/SmartMedia */ 63 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 64 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2), 65 &smc->cs[3].setup); 66 67 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 68 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 69 &smc->cs[3].pulse); 70 71 writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6), 72 &smc->cs[3].cycle); 73 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 74 AT91_SMC_MODE_EXNW_DISABLE | 75 AT91_SMC_MODE_DBW_8 | 76 AT91_SMC_MODE_TDF_CYCLE(12), 77 &smc->cs[3].mode); 78 79 /* Configure RDY/BSY */ 80 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); 81 82 /* Enable NandFlash */ 83 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 84 } 85 #endif /* CONFIG_CMD_NAND */ 86 87 #ifdef CONFIG_MACB 88 static void meesc_macb_hw_init(void) 89 { 90 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; 91 /* Enable clock */ 92 writel(1 << ATMEL_ID_EMAC, &pmc->pcer); 93 at91_macb_hw_init(); 94 } 95 #endif 96 97 /* 98 * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT 99 * controller debugging 100 * The ET1100 is located at physical address 0x70000000 101 * Its process memory is located at physical address 0x70001000 102 */ 103 static void meesc_ethercat_hw_init(void) 104 { 105 at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1; 106 107 /* Configure SMC EBI1_CS0 for EtherCAT */ 108 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | 109 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0), 110 &smc1->cs[0].setup); 111 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) | 112 AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9), 113 &smc1->cs[0].pulse); 114 writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6), 115 &smc1->cs[0].cycle); 116 /* 117 * Configure behavior at external wait signal, byte-select mode, 16 bit 118 * data bus width, none data float wait states and TDF optimization 119 */ 120 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY | 121 AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) | 122 AT91_SMC_MODE_TDF, &smc1->cs[0].mode); 123 124 /* Configure RDY/BSY */ 125 at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */ 126 } 127 128 int dram_init(void) 129 { 130 /* dram_init must store complete ramsize in gd->ram_size */ 131 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, 132 PHYS_SDRAM_SIZE); 133 return 0; 134 } 135 136 void dram_init_banksize(void) 137 { 138 gd->bd->bi_dram[0].start = PHYS_SDRAM; 139 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 140 } 141 142 int board_eth_init(bd_t *bis) 143 { 144 int rc = 0; 145 #ifdef CONFIG_MACB 146 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); 147 #endif 148 return rc; 149 } 150 151 #ifdef CONFIG_DISPLAY_BOARDINFO 152 int checkboard(void) 153 { 154 char str[32]; 155 u_char hw_type; /* hardware type */ 156 157 /* read the "Type" register of the ET1100 controller */ 158 hw_type = readb(CONFIG_ET1100_BASE); 159 160 switch (hw_type) { 161 case 0x11: 162 case 0x3F: 163 /* ET1100 present, arch number of MEESC-Board */ 164 gd->bd->bi_arch_number = MACH_TYPE_MEESC; 165 puts("Board: CAN-EtherCAT Gateway"); 166 break; 167 case 0xFF: 168 /* no ET1100 present, arch number of EtherCAN/2-Board */ 169 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2; 170 puts("Board: EtherCAN/2 Gateway"); 171 /* switch on LED1D */ 172 at91_set_pio_output(AT91_PIO_PORTB, 12, 1); 173 break; 174 default: 175 /* assume, no ET1100 present, arch number of EtherCAN/2-Board */ 176 gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2; 177 printf("ERROR! Read invalid hw_type: %02X\n", hw_type); 178 puts("Board: EtherCAN/2 Gateway"); 179 break; 180 } 181 if (getenv_f("serial#", str, sizeof(str)) > 0) { 182 puts(", serial# "); 183 puts(str); 184 } 185 #ifdef CONFIG_REVISION_TAG 186 printf("\nHardware-revision: 1.%d\n", get_hw_rev()); 187 #endif 188 printf("Mach-type: %lu\n", gd->bd->bi_arch_number); 189 return 0; 190 } 191 #endif /* CONFIG_DISPLAY_BOARDINFO */ 192 193 #ifdef CONFIG_SERIAL_TAG 194 void get_board_serial(struct tag_serialnr *serialnr) 195 { 196 char *str; 197 198 char *serial = getenv("serial#"); 199 if (serial) { 200 str = strchr(serial, '_'); 201 if (str && (strlen(str) >= 4)) { 202 serialnr->high = (*(str + 1) << 8) | *(str + 2); 203 serialnr->low = simple_strtoul(str + 3, NULL, 16); 204 } 205 } else { 206 serialnr->high = 0; 207 serialnr->low = 0; 208 } 209 } 210 #endif 211 212 #ifdef CONFIG_REVISION_TAG 213 u32 get_board_rev(void) 214 { 215 return hw_rev | 0x100; 216 } 217 #endif 218 219 #ifdef CONFIG_MISC_INIT_R 220 int misc_init_r(void) 221 { 222 char *str; 223 char buf[32]; 224 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; 225 226 /* 227 * Normally the processor clock has a divisor of 2. 228 * In some cases this this needs to be set to 4. 229 * Check the user has set environment mdiv to 4 to change the divisor. 230 */ 231 if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) { 232 writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) | 233 AT91SAM9_PMC_MDIV_4, &pmc->mckr); 234 at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); 235 serial_setbrg(); 236 /* Notify the user that the clock is not default */ 237 printf("Setting master clock to %s MHz\n", 238 strmhz(buf, get_mck_clk_rate())); 239 } 240 241 return 0; 242 } 243 #endif /* CONFIG_MISC_INIT_R */ 244 245 int board_early_init_f(void) 246 { 247 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; 248 249 /* enable all clocks */ 250 writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | 251 (1 << ATMEL_ID_PIOCDE) | (1 << ATMEL_ID_UHP), 252 &pmc->pcer); 253 254 at91_seriald_hw_init(); 255 256 return 0; 257 } 258 259 int board_init(void) 260 { 261 /* initialize ET1100 Controller */ 262 meesc_ethercat_hw_init(); 263 264 /* adress of boot parameters */ 265 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 266 267 #ifdef CONFIG_CMD_NAND 268 meesc_nand_hw_init(); 269 #endif 270 #ifdef CONFIG_HAS_DATAFLASH 271 at91_spi0_hw_init(1 << 0); 272 #endif 273 #ifdef CONFIG_MACB 274 meesc_macb_hw_init(); 275 #endif 276 #ifdef CONFIG_AT91_CAN 277 at91_can_hw_init(); 278 #endif 279 #ifdef CONFIG_USB_OHCI_NEW 280 at91_uhp_hw_init(); 281 #endif 282 return 0; 283 } 284