1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2016 Amarula Solutions B.V. 4 * Copyright (C) 2016 Engicam S.r.l. 5 * Author: Jagan Teki <jagan@amarulasolutions.com> 6 */ 7 8 #include <common.h> 9 #include <mmc.h> 10 11 #include <asm/io.h> 12 #include <asm/gpio.h> 13 #include <linux/sizes.h> 14 15 #include <asm/arch/clock.h> 16 #include <asm/arch/crm_regs.h> 17 #include <asm/arch/iomux.h> 18 #include <asm/arch/mx6-pins.h> 19 #include <asm/arch/sys_proto.h> 20 #include <asm/mach-imx/iomux-v3.h> 21 22 #include "../common/board.h" 23 24 #ifdef CONFIG_NAND_MXS 25 26 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) 27 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ 28 PAD_CTL_SRE_FAST) 29 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) 30 31 static iomux_v3_cfg_t const nand_pads[] = { 32 IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 33 IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 34 IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 35 IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 36 IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 37 IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 38 IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 39 IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 40 IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 41 IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 42 IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 43 IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 44 IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 45 IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 46 IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), 47 }; 48 49 void setup_gpmi_nand(void) 50 { 51 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 52 53 /* config gpmi nand iomux */ 54 SETUP_IOMUX_PADS(nand_pads); 55 56 clrbits_le32(&mxc_ccm->CCGR4, 57 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 58 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 59 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 60 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 61 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); 62 63 /* 64 * config gpmi and bch clock to 100 MHz 65 * bch/gpmi select PLL2 PFD2 400M 66 * 100M = 400M / 4 67 */ 68 clrbits_le32(&mxc_ccm->cscmr1, 69 MXC_CCM_CSCMR1_BCH_CLK_SEL | 70 MXC_CCM_CSCMR1_GPMI_CLK_SEL); 71 clrsetbits_le32(&mxc_ccm->cscdr1, 72 MXC_CCM_CSCDR1_BCH_PODF_MASK | 73 MXC_CCM_CSCDR1_GPMI_PODF_MASK, 74 (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | 75 (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); 76 77 /* enable gpmi and bch clock gating */ 78 setbits_le32(&mxc_ccm->CCGR4, 79 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 80 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 81 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 82 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 83 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); 84 85 /* enable apbh clock gating */ 86 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 87 } 88 #endif /* CONFIG_NAND_MXS */ 89 90 #ifdef CONFIG_ENV_IS_IN_MMC 91 int board_mmc_get_env_dev(int devno) 92 { 93 /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */ 94 return (devno == 0) ? 0 : 1; 95 } 96 #endif 97