1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2016 Amarula Solutions B.V. 4 * Copyright (C) 2016 Engicam S.r.l. 5 * Author: Jagan Teki <jagan@amarulasolutions.com> 6 */ 7 8 #include <common.h> 9 #include <spl.h> 10 11 #include <asm/io.h> 12 #include <asm/gpio.h> 13 #include <linux/sizes.h> 14 15 #include <asm/arch/clock.h> 16 #include <asm/arch/crm_regs.h> 17 #include <asm/arch/iomux.h> 18 #include <asm/arch/mx6-ddr.h> 19 #include <asm/arch/mx6-pins.h> 20 #include <asm/arch/sys_proto.h> 21 22 #include <asm/mach-imx/iomux-v3.h> 23 #include <asm/mach-imx/video.h> 24 25 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 26 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 27 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 28 29 static iomux_v3_cfg_t const uart_pads[] = { 30 #ifdef CONFIG_MX6QDL 31 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 32 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 33 #elif CONFIG_MX6UL 34 IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)), 35 IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)), 36 #endif 37 }; 38 39 #ifdef CONFIG_SPL_LOAD_FIT 40 int board_fit_config_name_match(const char *name) 41 { 42 if (is_mx6dq() && !strcmp(name, "imx6q-icore")) 43 return 0; 44 else if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs")) 45 return 0; 46 else if (is_mx6dq() && !strcmp(name, "imx6q-icore-mipi")) 47 return 0; 48 else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore")) 49 return 0; 50 else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs")) 51 return 0; 52 else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-mipi")) 53 return 0; 54 else 55 return -1; 56 } 57 #endif 58 59 #ifdef CONFIG_ENV_IS_IN_MMC 60 void board_boot_order(u32 *spl_boot_list) 61 { 62 u32 bmode = imx6_src_get_boot_mode(); 63 u8 boot_dev = BOOT_DEVICE_MMC1; 64 65 switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) { 66 case IMX6_BMODE_SD: 67 case IMX6_BMODE_ESD: 68 /* SD/eSD - BOOT_DEVICE_MMC1 */ 69 break; 70 case IMX6_BMODE_MMC: 71 case IMX6_BMODE_EMMC: 72 /* MMC/eMMC */ 73 boot_dev = BOOT_DEVICE_MMC2; 74 break; 75 default: 76 /* Default - BOOT_DEVICE_MMC1 */ 77 printf("Wrong board boot order\n"); 78 break; 79 } 80 81 spl_boot_list[0] = boot_dev; 82 } 83 #endif 84 85 #ifdef CONFIG_SPL_OS_BOOT 86 int spl_start_uboot(void) 87 { 88 /* break into full u-boot on 'c' */ 89 if (serial_tstc() && serial_getc() == 'c') 90 return 1; 91 92 return 0; 93 } 94 #endif 95 96 #ifdef CONFIG_MX6QDL 97 /* 98 * Driving strength: 99 * 0x30 == 40 Ohm 100 * 0x28 == 48 Ohm 101 */ 102 #define IMX6DQ_DRIVE_STRENGTH 0x30 103 #define IMX6SDL_DRIVE_STRENGTH 0x28 104 105 /* configure MX6Q/DUAL mmdc DDR io registers */ 106 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { 107 .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, 108 .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, 109 .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, 110 .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, 111 .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, 112 .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, 113 .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, 114 .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, 115 .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, 116 .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, 117 .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, 118 .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, 119 .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, 120 .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, 121 .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, 122 .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, 123 .dram_cas = IMX6DQ_DRIVE_STRENGTH, 124 .dram_ras = IMX6DQ_DRIVE_STRENGTH, 125 .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, 126 .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, 127 .dram_reset = IMX6DQ_DRIVE_STRENGTH, 128 .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH, 129 .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH, 130 .dram_sdba2 = 0x00000000, 131 .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, 132 .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, 133 }; 134 135 /* configure MX6Q/DUAL mmdc GRP io registers */ 136 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { 137 .grp_b0ds = IMX6DQ_DRIVE_STRENGTH, 138 .grp_b1ds = IMX6DQ_DRIVE_STRENGTH, 139 .grp_b2ds = IMX6DQ_DRIVE_STRENGTH, 140 .grp_b3ds = IMX6DQ_DRIVE_STRENGTH, 141 .grp_b4ds = IMX6DQ_DRIVE_STRENGTH, 142 .grp_b5ds = IMX6DQ_DRIVE_STRENGTH, 143 .grp_b6ds = IMX6DQ_DRIVE_STRENGTH, 144 .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, 145 .grp_addds = IMX6DQ_DRIVE_STRENGTH, 146 .grp_ddrmode_ctl = 0x00020000, 147 .grp_ddrpke = 0x00000000, 148 .grp_ddrmode = 0x00020000, 149 .grp_ctlds = IMX6DQ_DRIVE_STRENGTH, 150 .grp_ddr_type = 0x000c0000, 151 }; 152 153 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ 154 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { 155 .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, 156 .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, 157 .dram_cas = IMX6SDL_DRIVE_STRENGTH, 158 .dram_ras = IMX6SDL_DRIVE_STRENGTH, 159 .dram_reset = IMX6SDL_DRIVE_STRENGTH, 160 .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, 161 .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, 162 .dram_sdba2 = 0x00000000, 163 .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, 164 .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, 165 .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, 166 .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, 167 .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, 168 .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, 169 .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, 170 .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, 171 .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, 172 .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, 173 .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, 174 .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, 175 .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, 176 .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, 177 .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, 178 .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, 179 .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, 180 .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, 181 }; 182 183 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ 184 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { 185 .grp_ddr_type = 0x000c0000, 186 .grp_ddrmode_ctl = 0x00020000, 187 .grp_ddrpke = 0x00000000, 188 .grp_addds = IMX6SDL_DRIVE_STRENGTH, 189 .grp_ctlds = IMX6SDL_DRIVE_STRENGTH, 190 .grp_ddrmode = 0x00020000, 191 .grp_b0ds = IMX6SDL_DRIVE_STRENGTH, 192 .grp_b1ds = IMX6SDL_DRIVE_STRENGTH, 193 .grp_b2ds = IMX6SDL_DRIVE_STRENGTH, 194 .grp_b3ds = IMX6SDL_DRIVE_STRENGTH, 195 .grp_b4ds = IMX6SDL_DRIVE_STRENGTH, 196 .grp_b5ds = IMX6SDL_DRIVE_STRENGTH, 197 .grp_b6ds = IMX6SDL_DRIVE_STRENGTH, 198 .grp_b7ds = IMX6SDL_DRIVE_STRENGTH, 199 }; 200 201 /* mt41j256 */ 202 static struct mx6_ddr3_cfg mt41j256 = { 203 .mem_speed = 1066, 204 .density = 2, 205 .width = 16, 206 .banks = 8, 207 .rowaddr = 13, 208 .coladdr = 10, 209 .pagesz = 2, 210 .trcd = 1375, 211 .trcmin = 4875, 212 .trasmin = 3500, 213 .SRT = 0, 214 }; 215 216 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { 217 .p0_mpwldectrl0 = 0x000E0009, 218 .p0_mpwldectrl1 = 0x0018000E, 219 .p1_mpwldectrl0 = 0x00000007, 220 .p1_mpwldectrl1 = 0x00000000, 221 .p0_mpdgctrl0 = 0x43280334, 222 .p0_mpdgctrl1 = 0x031C0314, 223 .p1_mpdgctrl0 = 0x4318031C, 224 .p1_mpdgctrl1 = 0x030C0258, 225 .p0_mprddlctl = 0x3E343A40, 226 .p1_mprddlctl = 0x383C3844, 227 .p0_mpwrdlctl = 0x40404440, 228 .p1_mpwrdlctl = 0x4C3E4446, 229 }; 230 231 /* DDR 64bit */ 232 static struct mx6_ddr_sysinfo mem_q = { 233 .ddr_type = DDR_TYPE_DDR3, 234 .dsize = 2, 235 .cs1_mirror = 0, 236 /* config for full 4GB range so that get_mem_size() works */ 237 .cs_density = 32, 238 .ncs = 1, 239 .bi_on = 1, 240 .rtt_nom = 2, 241 .rtt_wr = 2, 242 .ralat = 5, 243 .walat = 0, 244 .mif3_mode = 3, 245 .rst_to_cke = 0x23, 246 .sde_to_rst = 0x10, 247 }; 248 249 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { 250 .p0_mpwldectrl0 = 0x001F0024, 251 .p0_mpwldectrl1 = 0x00110018, 252 .p1_mpwldectrl0 = 0x001F0024, 253 .p1_mpwldectrl1 = 0x00110018, 254 .p0_mpdgctrl0 = 0x4230022C, 255 .p0_mpdgctrl1 = 0x02180220, 256 .p1_mpdgctrl0 = 0x42440248, 257 .p1_mpdgctrl1 = 0x02300238, 258 .p0_mprddlctl = 0x44444A48, 259 .p1_mprddlctl = 0x46484A42, 260 .p0_mpwrdlctl = 0x38383234, 261 .p1_mpwrdlctl = 0x3C34362E, 262 }; 263 264 /* DDR 64bit 1GB */ 265 static struct mx6_ddr_sysinfo mem_dl = { 266 .dsize = 2, 267 .cs1_mirror = 0, 268 /* config for full 4GB range so that get_mem_size() works */ 269 .cs_density = 32, 270 .ncs = 1, 271 .bi_on = 1, 272 .rtt_nom = 1, 273 .rtt_wr = 1, 274 .ralat = 5, 275 .walat = 0, 276 .mif3_mode = 3, 277 .rst_to_cke = 0x23, 278 .sde_to_rst = 0x10, 279 }; 280 281 /* DDR 32bit 512MB */ 282 static struct mx6_ddr_sysinfo mem_s = { 283 .dsize = 1, 284 .cs1_mirror = 0, 285 /* config for full 4GB range so that get_mem_size() works */ 286 .cs_density = 32, 287 .ncs = 1, 288 .bi_on = 1, 289 .rtt_nom = 1, 290 .rtt_wr = 1, 291 .ralat = 5, 292 .walat = 0, 293 .mif3_mode = 3, 294 .rst_to_cke = 0x23, 295 .sde_to_rst = 0x10, 296 }; 297 #endif /* CONFIG_MX6QDL */ 298 299 #ifdef CONFIG_MX6UL 300 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { 301 .grp_addds = 0x00000030, 302 .grp_ddrmode_ctl = 0x00020000, 303 .grp_b0ds = 0x00000030, 304 .grp_ctlds = 0x00000030, 305 .grp_b1ds = 0x00000030, 306 .grp_ddrpke = 0x00000000, 307 .grp_ddrmode = 0x00020000, 308 .grp_ddr_type = 0x000c0000, 309 }; 310 311 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 312 .dram_dqm0 = 0x00000030, 313 .dram_dqm1 = 0x00000030, 314 .dram_ras = 0x00000030, 315 .dram_cas = 0x00000030, 316 .dram_odt0 = 0x00000030, 317 .dram_odt1 = 0x00000030, 318 .dram_sdba2 = 0x00000000, 319 .dram_sdclk_0 = 0x00000008, 320 .dram_sdqs0 = 0x00000038, 321 .dram_sdqs1 = 0x00000030, 322 .dram_reset = 0x00000030, 323 }; 324 325 static struct mx6_mmdc_calibration mx6_mmcd_calib = { 326 .p0_mpwldectrl0 = 0x00070007, 327 .p0_mpdgctrl0 = 0x41490145, 328 .p0_mprddlctl = 0x40404546, 329 .p0_mpwrdlctl = 0x4040524D, 330 }; 331 332 struct mx6_ddr_sysinfo ddr_sysinfo = { 333 .dsize = 0, 334 .cs_density = 20, 335 .ncs = 1, 336 .cs1_mirror = 0, 337 .rtt_wr = 2, 338 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 339 .walat = 1, /* Write additional latency */ 340 .ralat = 5, /* Read additional latency */ 341 .mif3_mode = 3, /* Command prediction working mode */ 342 .bi_on = 1, /* Bank interleaving enabled */ 343 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 344 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 345 .ddr_type = DDR_TYPE_DDR3, 346 }; 347 348 static struct mx6_ddr3_cfg mem_ddr = { 349 .mem_speed = 800, 350 .density = 4, 351 .width = 16, 352 .banks = 8, 353 #ifdef TARGET_MX6UL_ISIOT 354 .rowaddr = 15, 355 #else 356 .rowaddr = 13, 357 #endif 358 .coladdr = 10, 359 .pagesz = 2, 360 .trcd = 1375, 361 .trcmin = 4875, 362 .trasmin = 3500, 363 }; 364 #endif /* CONFIG_MX6UL */ 365 366 static void ccgr_init(void) 367 { 368 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 369 370 #ifdef CONFIG_MX6QDL 371 writel(0x00003F3F, &ccm->CCGR0); 372 writel(0x0030FC00, &ccm->CCGR1); 373 writel(0x000FC000, &ccm->CCGR2); 374 writel(0x3F300000, &ccm->CCGR3); 375 writel(0xFF00F300, &ccm->CCGR4); 376 writel(0x0F0000C3, &ccm->CCGR5); 377 writel(0x000003CC, &ccm->CCGR6); 378 #elif CONFIG_MX6UL 379 writel(0x00c03f3f, &ccm->CCGR0); 380 writel(0xfcffff00, &ccm->CCGR1); 381 writel(0x0cffffcc, &ccm->CCGR2); 382 writel(0x3f3c3030, &ccm->CCGR3); 383 writel(0xff00fffc, &ccm->CCGR4); 384 writel(0x033f30ff, &ccm->CCGR5); 385 writel(0x00c00fff, &ccm->CCGR6); 386 #endif 387 } 388 389 static void spl_dram_init(void) 390 { 391 #ifdef CONFIG_MX6QDL 392 if (is_mx6solo()) { 393 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 394 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); 395 } else if (is_mx6dl()) { 396 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 397 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); 398 } else if (is_mx6dq()) { 399 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); 400 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); 401 } 402 #elif CONFIG_MX6UL 403 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 404 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); 405 #endif 406 407 udelay(100); 408 } 409 410 void board_init_f(ulong dummy) 411 { 412 ccgr_init(); 413 414 /* setup AIPS and disable watchdog */ 415 arch_cpu_init(); 416 417 if (!(is_mx6ul())) 418 gpr_init(); 419 420 /* iomux */ 421 SETUP_IOMUX_PADS(uart_pads); 422 423 /* setup GP timer */ 424 timer_init(); 425 426 /* UART clocks enabled and gd valid - init serial console */ 427 preloader_console_init(); 428 429 /* DDR initialization */ 430 spl_dram_init(); 431 } 432