1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2016 Amarula Solutions B.V. 4 * Copyright (C) 2016 Engicam S.r.l. 5 * Author: Jagan Teki <jagan@amarulasolutions.com> 6 */ 7 8 #include <common.h> 9 #include <spl.h> 10 11 #include <asm/io.h> 12 #include <asm/gpio.h> 13 #include <linux/sizes.h> 14 15 #include <asm/arch/clock.h> 16 #include <asm/arch/crm_regs.h> 17 #include <asm/arch/iomux.h> 18 #include <asm/arch/mx6-ddr.h> 19 #include <asm/arch/mx6-pins.h> 20 #include <asm/arch/sys_proto.h> 21 22 #include <asm/mach-imx/iomux-v3.h> 23 #include <asm/mach-imx/video.h> 24 25 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 26 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 27 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 28 29 static iomux_v3_cfg_t const uart_pads[] = { 30 #ifdef CONFIG_MX6QDL 31 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 32 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 33 #elif CONFIG_MX6UL 34 IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)), 35 IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)), 36 #endif 37 }; 38 39 #ifdef CONFIG_SPL_LOAD_FIT 40 int board_fit_config_name_match(const char *name) 41 { 42 if (is_mx6dq() && !strcmp(name, "imx6q-icore")) 43 return 0; 44 else if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs")) 45 return 0; 46 else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore")) 47 return 0; 48 else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs")) 49 return 0; 50 else 51 return -1; 52 } 53 #endif 54 55 #ifdef CONFIG_ENV_IS_IN_MMC 56 void board_boot_order(u32 *spl_boot_list) 57 { 58 u32 bmode = imx6_src_get_boot_mode(); 59 u8 boot_dev = BOOT_DEVICE_MMC1; 60 61 switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) { 62 case IMX6_BMODE_SD: 63 case IMX6_BMODE_ESD: 64 /* SD/eSD - BOOT_DEVICE_MMC1 */ 65 break; 66 case IMX6_BMODE_MMC: 67 case IMX6_BMODE_EMMC: 68 /* MMC/eMMC */ 69 boot_dev = BOOT_DEVICE_MMC2; 70 break; 71 default: 72 /* Default - BOOT_DEVICE_MMC1 */ 73 printf("Wrong board boot order\n"); 74 break; 75 } 76 77 spl_boot_list[0] = boot_dev; 78 } 79 #endif 80 81 #ifdef CONFIG_SPL_OS_BOOT 82 int spl_start_uboot(void) 83 { 84 /* break into full u-boot on 'c' */ 85 if (serial_tstc() && serial_getc() == 'c') 86 return 1; 87 88 return 0; 89 } 90 #endif 91 92 #ifdef CONFIG_MX6QDL 93 /* 94 * Driving strength: 95 * 0x30 == 40 Ohm 96 * 0x28 == 48 Ohm 97 */ 98 #define IMX6DQ_DRIVE_STRENGTH 0x30 99 #define IMX6SDL_DRIVE_STRENGTH 0x28 100 101 /* configure MX6Q/DUAL mmdc DDR io registers */ 102 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { 103 .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, 104 .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, 105 .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, 106 .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, 107 .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, 108 .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, 109 .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, 110 .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, 111 .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, 112 .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, 113 .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, 114 .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, 115 .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, 116 .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, 117 .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, 118 .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, 119 .dram_cas = IMX6DQ_DRIVE_STRENGTH, 120 .dram_ras = IMX6DQ_DRIVE_STRENGTH, 121 .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, 122 .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, 123 .dram_reset = IMX6DQ_DRIVE_STRENGTH, 124 .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH, 125 .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH, 126 .dram_sdba2 = 0x00000000, 127 .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, 128 .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, 129 }; 130 131 /* configure MX6Q/DUAL mmdc GRP io registers */ 132 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { 133 .grp_b0ds = IMX6DQ_DRIVE_STRENGTH, 134 .grp_b1ds = IMX6DQ_DRIVE_STRENGTH, 135 .grp_b2ds = IMX6DQ_DRIVE_STRENGTH, 136 .grp_b3ds = IMX6DQ_DRIVE_STRENGTH, 137 .grp_b4ds = IMX6DQ_DRIVE_STRENGTH, 138 .grp_b5ds = IMX6DQ_DRIVE_STRENGTH, 139 .grp_b6ds = IMX6DQ_DRIVE_STRENGTH, 140 .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, 141 .grp_addds = IMX6DQ_DRIVE_STRENGTH, 142 .grp_ddrmode_ctl = 0x00020000, 143 .grp_ddrpke = 0x00000000, 144 .grp_ddrmode = 0x00020000, 145 .grp_ctlds = IMX6DQ_DRIVE_STRENGTH, 146 .grp_ddr_type = 0x000c0000, 147 }; 148 149 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ 150 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { 151 .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, 152 .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, 153 .dram_cas = IMX6SDL_DRIVE_STRENGTH, 154 .dram_ras = IMX6SDL_DRIVE_STRENGTH, 155 .dram_reset = IMX6SDL_DRIVE_STRENGTH, 156 .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, 157 .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, 158 .dram_sdba2 = 0x00000000, 159 .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, 160 .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, 161 .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, 162 .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, 163 .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, 164 .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, 165 .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, 166 .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, 167 .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, 168 .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, 169 .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, 170 .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, 171 .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, 172 .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, 173 .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, 174 .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, 175 .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, 176 .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, 177 }; 178 179 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ 180 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { 181 .grp_ddr_type = 0x000c0000, 182 .grp_ddrmode_ctl = 0x00020000, 183 .grp_ddrpke = 0x00000000, 184 .grp_addds = IMX6SDL_DRIVE_STRENGTH, 185 .grp_ctlds = IMX6SDL_DRIVE_STRENGTH, 186 .grp_ddrmode = 0x00020000, 187 .grp_b0ds = IMX6SDL_DRIVE_STRENGTH, 188 .grp_b1ds = IMX6SDL_DRIVE_STRENGTH, 189 .grp_b2ds = IMX6SDL_DRIVE_STRENGTH, 190 .grp_b3ds = IMX6SDL_DRIVE_STRENGTH, 191 .grp_b4ds = IMX6SDL_DRIVE_STRENGTH, 192 .grp_b5ds = IMX6SDL_DRIVE_STRENGTH, 193 .grp_b6ds = IMX6SDL_DRIVE_STRENGTH, 194 .grp_b7ds = IMX6SDL_DRIVE_STRENGTH, 195 }; 196 197 /* mt41j256 */ 198 static struct mx6_ddr3_cfg mt41j256 = { 199 .mem_speed = 1066, 200 .density = 2, 201 .width = 16, 202 .banks = 8, 203 .rowaddr = 13, 204 .coladdr = 10, 205 .pagesz = 2, 206 .trcd = 1375, 207 .trcmin = 4875, 208 .trasmin = 3500, 209 .SRT = 0, 210 }; 211 212 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { 213 .p0_mpwldectrl0 = 0x000E0009, 214 .p0_mpwldectrl1 = 0x0018000E, 215 .p1_mpwldectrl0 = 0x00000007, 216 .p1_mpwldectrl1 = 0x00000000, 217 .p0_mpdgctrl0 = 0x43280334, 218 .p0_mpdgctrl1 = 0x031C0314, 219 .p1_mpdgctrl0 = 0x4318031C, 220 .p1_mpdgctrl1 = 0x030C0258, 221 .p0_mprddlctl = 0x3E343A40, 222 .p1_mprddlctl = 0x383C3844, 223 .p0_mpwrdlctl = 0x40404440, 224 .p1_mpwrdlctl = 0x4C3E4446, 225 }; 226 227 /* DDR 64bit */ 228 static struct mx6_ddr_sysinfo mem_q = { 229 .ddr_type = DDR_TYPE_DDR3, 230 .dsize = 2, 231 .cs1_mirror = 0, 232 /* config for full 4GB range so that get_mem_size() works */ 233 .cs_density = 32, 234 .ncs = 1, 235 .bi_on = 1, 236 .rtt_nom = 2, 237 .rtt_wr = 2, 238 .ralat = 5, 239 .walat = 0, 240 .mif3_mode = 3, 241 .rst_to_cke = 0x23, 242 .sde_to_rst = 0x10, 243 }; 244 245 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { 246 .p0_mpwldectrl0 = 0x001F0024, 247 .p0_mpwldectrl1 = 0x00110018, 248 .p1_mpwldectrl0 = 0x001F0024, 249 .p1_mpwldectrl1 = 0x00110018, 250 .p0_mpdgctrl0 = 0x4230022C, 251 .p0_mpdgctrl1 = 0x02180220, 252 .p1_mpdgctrl0 = 0x42440248, 253 .p1_mpdgctrl1 = 0x02300238, 254 .p0_mprddlctl = 0x44444A48, 255 .p1_mprddlctl = 0x46484A42, 256 .p0_mpwrdlctl = 0x38383234, 257 .p1_mpwrdlctl = 0x3C34362E, 258 }; 259 260 /* DDR 64bit 1GB */ 261 static struct mx6_ddr_sysinfo mem_dl = { 262 .dsize = 2, 263 .cs1_mirror = 0, 264 /* config for full 4GB range so that get_mem_size() works */ 265 .cs_density = 32, 266 .ncs = 1, 267 .bi_on = 1, 268 .rtt_nom = 1, 269 .rtt_wr = 1, 270 .ralat = 5, 271 .walat = 0, 272 .mif3_mode = 3, 273 .rst_to_cke = 0x23, 274 .sde_to_rst = 0x10, 275 }; 276 277 /* DDR 32bit 512MB */ 278 static struct mx6_ddr_sysinfo mem_s = { 279 .dsize = 1, 280 .cs1_mirror = 0, 281 /* config for full 4GB range so that get_mem_size() works */ 282 .cs_density = 32, 283 .ncs = 1, 284 .bi_on = 1, 285 .rtt_nom = 1, 286 .rtt_wr = 1, 287 .ralat = 5, 288 .walat = 0, 289 .mif3_mode = 3, 290 .rst_to_cke = 0x23, 291 .sde_to_rst = 0x10, 292 }; 293 #endif /* CONFIG_MX6QDL */ 294 295 #ifdef CONFIG_MX6UL 296 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { 297 .grp_addds = 0x00000030, 298 .grp_ddrmode_ctl = 0x00020000, 299 .grp_b0ds = 0x00000030, 300 .grp_ctlds = 0x00000030, 301 .grp_b1ds = 0x00000030, 302 .grp_ddrpke = 0x00000000, 303 .grp_ddrmode = 0x00020000, 304 .grp_ddr_type = 0x000c0000, 305 }; 306 307 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 308 .dram_dqm0 = 0x00000030, 309 .dram_dqm1 = 0x00000030, 310 .dram_ras = 0x00000030, 311 .dram_cas = 0x00000030, 312 .dram_odt0 = 0x00000030, 313 .dram_odt1 = 0x00000030, 314 .dram_sdba2 = 0x00000000, 315 .dram_sdclk_0 = 0x00000008, 316 .dram_sdqs0 = 0x00000038, 317 .dram_sdqs1 = 0x00000030, 318 .dram_reset = 0x00000030, 319 }; 320 321 static struct mx6_mmdc_calibration mx6_mmcd_calib = { 322 .p0_mpwldectrl0 = 0x00070007, 323 .p0_mpdgctrl0 = 0x41490145, 324 .p0_mprddlctl = 0x40404546, 325 .p0_mpwrdlctl = 0x4040524D, 326 }; 327 328 struct mx6_ddr_sysinfo ddr_sysinfo = { 329 .dsize = 0, 330 .cs_density = 20, 331 .ncs = 1, 332 .cs1_mirror = 0, 333 .rtt_wr = 2, 334 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 335 .walat = 1, /* Write additional latency */ 336 .ralat = 5, /* Read additional latency */ 337 .mif3_mode = 3, /* Command prediction working mode */ 338 .bi_on = 1, /* Bank interleaving enabled */ 339 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 340 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 341 .ddr_type = DDR_TYPE_DDR3, 342 }; 343 344 static struct mx6_ddr3_cfg mem_ddr = { 345 .mem_speed = 800, 346 .density = 4, 347 .width = 16, 348 .banks = 8, 349 #ifdef TARGET_MX6UL_ISIOT 350 .rowaddr = 15, 351 #else 352 .rowaddr = 13, 353 #endif 354 .coladdr = 10, 355 .pagesz = 2, 356 .trcd = 1375, 357 .trcmin = 4875, 358 .trasmin = 3500, 359 }; 360 #endif /* CONFIG_MX6UL */ 361 362 static void ccgr_init(void) 363 { 364 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 365 366 #ifdef CONFIG_MX6QDL 367 writel(0x00003F3F, &ccm->CCGR0); 368 writel(0x0030FC00, &ccm->CCGR1); 369 writel(0x000FC000, &ccm->CCGR2); 370 writel(0x3F300000, &ccm->CCGR3); 371 writel(0xFF00F300, &ccm->CCGR4); 372 writel(0x0F0000C3, &ccm->CCGR5); 373 writel(0x000003CC, &ccm->CCGR6); 374 #elif CONFIG_MX6UL 375 writel(0x00c03f3f, &ccm->CCGR0); 376 writel(0xfcffff00, &ccm->CCGR1); 377 writel(0x0cffffcc, &ccm->CCGR2); 378 writel(0x3f3c3030, &ccm->CCGR3); 379 writel(0xff00fffc, &ccm->CCGR4); 380 writel(0x033f30ff, &ccm->CCGR5); 381 writel(0x00c00fff, &ccm->CCGR6); 382 #endif 383 } 384 385 static void spl_dram_init(void) 386 { 387 #ifdef CONFIG_MX6QDL 388 if (is_mx6solo()) { 389 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 390 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); 391 } else if (is_mx6dl()) { 392 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 393 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); 394 } else if (is_mx6dq()) { 395 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); 396 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); 397 } 398 #elif CONFIG_MX6UL 399 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 400 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); 401 #endif 402 403 udelay(100); 404 } 405 406 void board_init_f(ulong dummy) 407 { 408 ccgr_init(); 409 410 /* setup AIPS and disable watchdog */ 411 arch_cpu_init(); 412 413 gpr_init(); 414 415 /* iomux */ 416 SETUP_IOMUX_PADS(uart_pads); 417 418 /* setup GP timer */ 419 timer_init(); 420 421 /* UART clocks enabled and gd valid - init serial console */ 422 preloader_console_init(); 423 424 /* DDR initialization */ 425 spl_dram_init(); 426 } 427