1*d8de3c73SJagan Teki /* 2*d8de3c73SJagan Teki * Copyright (C) 2016 Amarula Solutions B.V. 3*d8de3c73SJagan Teki * Copyright (C) 2016 Engicam S.r.l. 4*d8de3c73SJagan Teki * Author: Jagan Teki <jagan@amarulasolutions.com> 5*d8de3c73SJagan Teki * 6*d8de3c73SJagan Teki * SPDX-License-Identifier: GPL-2.0+ 7*d8de3c73SJagan Teki */ 8*d8de3c73SJagan Teki 9*d8de3c73SJagan Teki #include <common.h> 10*d8de3c73SJagan Teki #include <spl.h> 11*d8de3c73SJagan Teki 12*d8de3c73SJagan Teki #include <asm/io.h> 13*d8de3c73SJagan Teki #include <asm/gpio.h> 14*d8de3c73SJagan Teki #include <linux/sizes.h> 15*d8de3c73SJagan Teki 16*d8de3c73SJagan Teki #include <asm/arch/clock.h> 17*d8de3c73SJagan Teki #include <asm/arch/crm_regs.h> 18*d8de3c73SJagan Teki #include <asm/arch/iomux.h> 19*d8de3c73SJagan Teki #include <asm/arch/mx6-ddr.h> 20*d8de3c73SJagan Teki #include <asm/arch/mx6-pins.h> 21*d8de3c73SJagan Teki #include <asm/arch/sys_proto.h> 22*d8de3c73SJagan Teki 23*d8de3c73SJagan Teki #include <asm/imx-common/iomux-v3.h> 24*d8de3c73SJagan Teki #include <asm/imx-common/video.h> 25*d8de3c73SJagan Teki 26*d8de3c73SJagan Teki DECLARE_GLOBAL_DATA_PTR; 27*d8de3c73SJagan Teki 28*d8de3c73SJagan Teki #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 29*d8de3c73SJagan Teki PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 30*d8de3c73SJagan Teki PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 31*d8de3c73SJagan Teki 32*d8de3c73SJagan Teki static iomux_v3_cfg_t const uart4_pads[] = { 33*d8de3c73SJagan Teki IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 34*d8de3c73SJagan Teki IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 35*d8de3c73SJagan Teki }; 36*d8de3c73SJagan Teki 37*d8de3c73SJagan Teki /* 38*d8de3c73SJagan Teki * Driving strength: 39*d8de3c73SJagan Teki * 0x30 == 40 Ohm 40*d8de3c73SJagan Teki * 0x28 == 48 Ohm 41*d8de3c73SJagan Teki */ 42*d8de3c73SJagan Teki #define IMX6DQ_DRIVE_STRENGTH 0x30 43*d8de3c73SJagan Teki #define IMX6SDL_DRIVE_STRENGTH 0x28 44*d8de3c73SJagan Teki 45*d8de3c73SJagan Teki /* configure MX6Q/DUAL mmdc DDR io registers */ 46*d8de3c73SJagan Teki static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { 47*d8de3c73SJagan Teki .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, 48*d8de3c73SJagan Teki .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, 49*d8de3c73SJagan Teki .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, 50*d8de3c73SJagan Teki .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, 51*d8de3c73SJagan Teki .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, 52*d8de3c73SJagan Teki .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, 53*d8de3c73SJagan Teki .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, 54*d8de3c73SJagan Teki .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, 55*d8de3c73SJagan Teki .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, 56*d8de3c73SJagan Teki .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, 57*d8de3c73SJagan Teki .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, 58*d8de3c73SJagan Teki .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, 59*d8de3c73SJagan Teki .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, 60*d8de3c73SJagan Teki .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, 61*d8de3c73SJagan Teki .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, 62*d8de3c73SJagan Teki .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, 63*d8de3c73SJagan Teki .dram_cas = IMX6DQ_DRIVE_STRENGTH, 64*d8de3c73SJagan Teki .dram_ras = IMX6DQ_DRIVE_STRENGTH, 65*d8de3c73SJagan Teki .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, 66*d8de3c73SJagan Teki .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, 67*d8de3c73SJagan Teki .dram_reset = IMX6DQ_DRIVE_STRENGTH, 68*d8de3c73SJagan Teki .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH, 69*d8de3c73SJagan Teki .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH, 70*d8de3c73SJagan Teki .dram_sdba2 = 0x00000000, 71*d8de3c73SJagan Teki .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, 72*d8de3c73SJagan Teki .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, 73*d8de3c73SJagan Teki }; 74*d8de3c73SJagan Teki 75*d8de3c73SJagan Teki /* configure MX6Q/DUAL mmdc GRP io registers */ 76*d8de3c73SJagan Teki static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { 77*d8de3c73SJagan Teki .grp_b0ds = IMX6DQ_DRIVE_STRENGTH, 78*d8de3c73SJagan Teki .grp_b1ds = IMX6DQ_DRIVE_STRENGTH, 79*d8de3c73SJagan Teki .grp_b2ds = IMX6DQ_DRIVE_STRENGTH, 80*d8de3c73SJagan Teki .grp_b3ds = IMX6DQ_DRIVE_STRENGTH, 81*d8de3c73SJagan Teki .grp_b4ds = IMX6DQ_DRIVE_STRENGTH, 82*d8de3c73SJagan Teki .grp_b5ds = IMX6DQ_DRIVE_STRENGTH, 83*d8de3c73SJagan Teki .grp_b6ds = IMX6DQ_DRIVE_STRENGTH, 84*d8de3c73SJagan Teki .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, 85*d8de3c73SJagan Teki .grp_addds = IMX6DQ_DRIVE_STRENGTH, 86*d8de3c73SJagan Teki .grp_ddrmode_ctl = 0x00020000, 87*d8de3c73SJagan Teki .grp_ddrpke = 0x00000000, 88*d8de3c73SJagan Teki .grp_ddrmode = 0x00020000, 89*d8de3c73SJagan Teki .grp_ctlds = IMX6DQ_DRIVE_STRENGTH, 90*d8de3c73SJagan Teki .grp_ddr_type = 0x000c0000, 91*d8de3c73SJagan Teki }; 92*d8de3c73SJagan Teki 93*d8de3c73SJagan Teki /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ 94*d8de3c73SJagan Teki struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { 95*d8de3c73SJagan Teki .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, 96*d8de3c73SJagan Teki .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, 97*d8de3c73SJagan Teki .dram_cas = IMX6SDL_DRIVE_STRENGTH, 98*d8de3c73SJagan Teki .dram_ras = IMX6SDL_DRIVE_STRENGTH, 99*d8de3c73SJagan Teki .dram_reset = IMX6SDL_DRIVE_STRENGTH, 100*d8de3c73SJagan Teki .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, 101*d8de3c73SJagan Teki .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, 102*d8de3c73SJagan Teki .dram_sdba2 = 0x00000000, 103*d8de3c73SJagan Teki .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, 104*d8de3c73SJagan Teki .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, 105*d8de3c73SJagan Teki .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, 106*d8de3c73SJagan Teki .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, 107*d8de3c73SJagan Teki .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, 108*d8de3c73SJagan Teki .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, 109*d8de3c73SJagan Teki .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, 110*d8de3c73SJagan Teki .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, 111*d8de3c73SJagan Teki .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, 112*d8de3c73SJagan Teki .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, 113*d8de3c73SJagan Teki .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, 114*d8de3c73SJagan Teki .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, 115*d8de3c73SJagan Teki .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, 116*d8de3c73SJagan Teki .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, 117*d8de3c73SJagan Teki .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, 118*d8de3c73SJagan Teki .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, 119*d8de3c73SJagan Teki .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, 120*d8de3c73SJagan Teki .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, 121*d8de3c73SJagan Teki }; 122*d8de3c73SJagan Teki 123*d8de3c73SJagan Teki /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ 124*d8de3c73SJagan Teki struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { 125*d8de3c73SJagan Teki .grp_ddr_type = 0x000c0000, 126*d8de3c73SJagan Teki .grp_ddrmode_ctl = 0x00020000, 127*d8de3c73SJagan Teki .grp_ddrpke = 0x00000000, 128*d8de3c73SJagan Teki .grp_addds = IMX6SDL_DRIVE_STRENGTH, 129*d8de3c73SJagan Teki .grp_ctlds = IMX6SDL_DRIVE_STRENGTH, 130*d8de3c73SJagan Teki .grp_ddrmode = 0x00020000, 131*d8de3c73SJagan Teki .grp_b0ds = IMX6SDL_DRIVE_STRENGTH, 132*d8de3c73SJagan Teki .grp_b1ds = IMX6SDL_DRIVE_STRENGTH, 133*d8de3c73SJagan Teki .grp_b2ds = IMX6SDL_DRIVE_STRENGTH, 134*d8de3c73SJagan Teki .grp_b3ds = IMX6SDL_DRIVE_STRENGTH, 135*d8de3c73SJagan Teki .grp_b4ds = IMX6SDL_DRIVE_STRENGTH, 136*d8de3c73SJagan Teki .grp_b5ds = IMX6SDL_DRIVE_STRENGTH, 137*d8de3c73SJagan Teki .grp_b6ds = IMX6SDL_DRIVE_STRENGTH, 138*d8de3c73SJagan Teki .grp_b7ds = IMX6SDL_DRIVE_STRENGTH, 139*d8de3c73SJagan Teki }; 140*d8de3c73SJagan Teki 141*d8de3c73SJagan Teki /* mt41j256 */ 142*d8de3c73SJagan Teki static struct mx6_ddr3_cfg mt41j256 = { 143*d8de3c73SJagan Teki .mem_speed = 1066, 144*d8de3c73SJagan Teki .density = 2, 145*d8de3c73SJagan Teki .width = 16, 146*d8de3c73SJagan Teki .banks = 8, 147*d8de3c73SJagan Teki .rowaddr = 13, 148*d8de3c73SJagan Teki .coladdr = 10, 149*d8de3c73SJagan Teki .pagesz = 2, 150*d8de3c73SJagan Teki .trcd = 1375, 151*d8de3c73SJagan Teki .trcmin = 4875, 152*d8de3c73SJagan Teki .trasmin = 3500, 153*d8de3c73SJagan Teki .SRT = 0, 154*d8de3c73SJagan Teki }; 155*d8de3c73SJagan Teki 156*d8de3c73SJagan Teki static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { 157*d8de3c73SJagan Teki .p0_mpwldectrl0 = 0x000E0009, 158*d8de3c73SJagan Teki .p0_mpwldectrl1 = 0x0018000E, 159*d8de3c73SJagan Teki .p1_mpwldectrl0 = 0x00000007, 160*d8de3c73SJagan Teki .p1_mpwldectrl1 = 0x00000000, 161*d8de3c73SJagan Teki .p0_mpdgctrl0 = 0x43280334, 162*d8de3c73SJagan Teki .p0_mpdgctrl1 = 0x031C0314, 163*d8de3c73SJagan Teki .p1_mpdgctrl0 = 0x4318031C, 164*d8de3c73SJagan Teki .p1_mpdgctrl1 = 0x030C0258, 165*d8de3c73SJagan Teki .p0_mprddlctl = 0x3E343A40, 166*d8de3c73SJagan Teki .p1_mprddlctl = 0x383C3844, 167*d8de3c73SJagan Teki .p0_mpwrdlctl = 0x40404440, 168*d8de3c73SJagan Teki .p1_mpwrdlctl = 0x4C3E4446, 169*d8de3c73SJagan Teki }; 170*d8de3c73SJagan Teki 171*d8de3c73SJagan Teki /* DDR 64bit */ 172*d8de3c73SJagan Teki static struct mx6_ddr_sysinfo mem_q = { 173*d8de3c73SJagan Teki .ddr_type = DDR_TYPE_DDR3, 174*d8de3c73SJagan Teki .dsize = 2, 175*d8de3c73SJagan Teki .cs1_mirror = 0, 176*d8de3c73SJagan Teki /* config for full 4GB range so that get_mem_size() works */ 177*d8de3c73SJagan Teki .cs_density = 32, 178*d8de3c73SJagan Teki .ncs = 1, 179*d8de3c73SJagan Teki .bi_on = 1, 180*d8de3c73SJagan Teki .rtt_nom = 2, 181*d8de3c73SJagan Teki .rtt_wr = 2, 182*d8de3c73SJagan Teki .ralat = 5, 183*d8de3c73SJagan Teki .walat = 0, 184*d8de3c73SJagan Teki .mif3_mode = 3, 185*d8de3c73SJagan Teki .rst_to_cke = 0x23, 186*d8de3c73SJagan Teki .sde_to_rst = 0x10, 187*d8de3c73SJagan Teki }; 188*d8de3c73SJagan Teki 189*d8de3c73SJagan Teki static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { 190*d8de3c73SJagan Teki .p0_mpwldectrl0 = 0x001F0024, 191*d8de3c73SJagan Teki .p0_mpwldectrl1 = 0x00110018, 192*d8de3c73SJagan Teki .p1_mpwldectrl0 = 0x001F0024, 193*d8de3c73SJagan Teki .p1_mpwldectrl1 = 0x00110018, 194*d8de3c73SJagan Teki .p0_mpdgctrl0 = 0x4230022C, 195*d8de3c73SJagan Teki .p0_mpdgctrl1 = 0x02180220, 196*d8de3c73SJagan Teki .p1_mpdgctrl0 = 0x42440248, 197*d8de3c73SJagan Teki .p1_mpdgctrl1 = 0x02300238, 198*d8de3c73SJagan Teki .p0_mprddlctl = 0x44444A48, 199*d8de3c73SJagan Teki .p1_mprddlctl = 0x46484A42, 200*d8de3c73SJagan Teki .p0_mpwrdlctl = 0x38383234, 201*d8de3c73SJagan Teki .p1_mpwrdlctl = 0x3C34362E, 202*d8de3c73SJagan Teki }; 203*d8de3c73SJagan Teki 204*d8de3c73SJagan Teki /* DDR 64bit 1GB */ 205*d8de3c73SJagan Teki static struct mx6_ddr_sysinfo mem_dl = { 206*d8de3c73SJagan Teki .dsize = 2, 207*d8de3c73SJagan Teki .cs1_mirror = 0, 208*d8de3c73SJagan Teki /* config for full 4GB range so that get_mem_size() works */ 209*d8de3c73SJagan Teki .cs_density = 32, 210*d8de3c73SJagan Teki .ncs = 1, 211*d8de3c73SJagan Teki .bi_on = 1, 212*d8de3c73SJagan Teki .rtt_nom = 1, 213*d8de3c73SJagan Teki .rtt_wr = 1, 214*d8de3c73SJagan Teki .ralat = 5, 215*d8de3c73SJagan Teki .walat = 0, 216*d8de3c73SJagan Teki .mif3_mode = 3, 217*d8de3c73SJagan Teki .rst_to_cke = 0x23, 218*d8de3c73SJagan Teki .sde_to_rst = 0x10, 219*d8de3c73SJagan Teki }; 220*d8de3c73SJagan Teki 221*d8de3c73SJagan Teki /* DDR 32bit 512MB */ 222*d8de3c73SJagan Teki static struct mx6_ddr_sysinfo mem_s = { 223*d8de3c73SJagan Teki .dsize = 1, 224*d8de3c73SJagan Teki .cs1_mirror = 0, 225*d8de3c73SJagan Teki /* config for full 4GB range so that get_mem_size() works */ 226*d8de3c73SJagan Teki .cs_density = 32, 227*d8de3c73SJagan Teki .ncs = 1, 228*d8de3c73SJagan Teki .bi_on = 1, 229*d8de3c73SJagan Teki .rtt_nom = 1, 230*d8de3c73SJagan Teki .rtt_wr = 1, 231*d8de3c73SJagan Teki .ralat = 5, 232*d8de3c73SJagan Teki .walat = 0, 233*d8de3c73SJagan Teki .mif3_mode = 3, 234*d8de3c73SJagan Teki .rst_to_cke = 0x23, 235*d8de3c73SJagan Teki .sde_to_rst = 0x10, 236*d8de3c73SJagan Teki }; 237*d8de3c73SJagan Teki 238*d8de3c73SJagan Teki static void ccgr_init(void) 239*d8de3c73SJagan Teki { 240*d8de3c73SJagan Teki struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 241*d8de3c73SJagan Teki 242*d8de3c73SJagan Teki writel(0x00003F3F, &ccm->CCGR0); 243*d8de3c73SJagan Teki writel(0x0030FC00, &ccm->CCGR1); 244*d8de3c73SJagan Teki writel(0x000FC000, &ccm->CCGR2); 245*d8de3c73SJagan Teki writel(0x3F300000, &ccm->CCGR3); 246*d8de3c73SJagan Teki writel(0xFF00F300, &ccm->CCGR4); 247*d8de3c73SJagan Teki writel(0x0F0000C3, &ccm->CCGR5); 248*d8de3c73SJagan Teki writel(0x000003CC, &ccm->CCGR6); 249*d8de3c73SJagan Teki } 250*d8de3c73SJagan Teki 251*d8de3c73SJagan Teki static void gpr_init(void) 252*d8de3c73SJagan Teki { 253*d8de3c73SJagan Teki struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 254*d8de3c73SJagan Teki 255*d8de3c73SJagan Teki /* enable AXI cache for VDOA/VPU/IPU */ 256*d8de3c73SJagan Teki writel(0xF00000CF, &iomux->gpr[4]); 257*d8de3c73SJagan Teki /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 258*d8de3c73SJagan Teki writel(0x007F007F, &iomux->gpr[6]); 259*d8de3c73SJagan Teki writel(0x007F007F, &iomux->gpr[7]); 260*d8de3c73SJagan Teki } 261*d8de3c73SJagan Teki 262*d8de3c73SJagan Teki static void spl_dram_init(void) 263*d8de3c73SJagan Teki { 264*d8de3c73SJagan Teki if (is_mx6solo()) { 265*d8de3c73SJagan Teki mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 266*d8de3c73SJagan Teki mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); 267*d8de3c73SJagan Teki } else if (is_mx6dl()) { 268*d8de3c73SJagan Teki mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 269*d8de3c73SJagan Teki mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); 270*d8de3c73SJagan Teki } else if (is_mx6dq()) { 271*d8de3c73SJagan Teki mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); 272*d8de3c73SJagan Teki mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); 273*d8de3c73SJagan Teki } 274*d8de3c73SJagan Teki 275*d8de3c73SJagan Teki udelay(100); 276*d8de3c73SJagan Teki } 277*d8de3c73SJagan Teki 278*d8de3c73SJagan Teki void board_init_f(ulong dummy) 279*d8de3c73SJagan Teki { 280*d8de3c73SJagan Teki ccgr_init(); 281*d8de3c73SJagan Teki 282*d8de3c73SJagan Teki /* setup AIPS and disable watchdog */ 283*d8de3c73SJagan Teki arch_cpu_init(); 284*d8de3c73SJagan Teki 285*d8de3c73SJagan Teki gpr_init(); 286*d8de3c73SJagan Teki 287*d8de3c73SJagan Teki /* iomux */ 288*d8de3c73SJagan Teki SETUP_IOMUX_PADS(uart4_pads); 289*d8de3c73SJagan Teki 290*d8de3c73SJagan Teki /* setup GP timer */ 291*d8de3c73SJagan Teki timer_init(); 292*d8de3c73SJagan Teki 293*d8de3c73SJagan Teki /* UART clocks enabled and gd valid - init serial console */ 294*d8de3c73SJagan Teki preloader_console_init(); 295*d8de3c73SJagan Teki 296*d8de3c73SJagan Teki /* DDR initialization */ 297*d8de3c73SJagan Teki spl_dram_init(); 298*d8de3c73SJagan Teki 299*d8de3c73SJagan Teki /* Clear the BSS. */ 300*d8de3c73SJagan Teki memset(__bss_start, 0, __bss_end - __bss_start); 301*d8de3c73SJagan Teki 302*d8de3c73SJagan Teki /* load/boot image from boot device */ 303*d8de3c73SJagan Teki board_init_r(NULL, 0); 304*d8de3c73SJagan Teki } 305