1d8de3c73SJagan Teki /* 2d8de3c73SJagan Teki * Copyright (C) 2016 Amarula Solutions B.V. 3d8de3c73SJagan Teki * Copyright (C) 2016 Engicam S.r.l. 4d8de3c73SJagan Teki * Author: Jagan Teki <jagan@amarulasolutions.com> 5d8de3c73SJagan Teki * 6d8de3c73SJagan Teki * SPDX-License-Identifier: GPL-2.0+ 7d8de3c73SJagan Teki */ 8d8de3c73SJagan Teki 9d8de3c73SJagan Teki #include <common.h> 10d8de3c73SJagan Teki #include <spl.h> 11d8de3c73SJagan Teki 12d8de3c73SJagan Teki #include <asm/io.h> 13d8de3c73SJagan Teki #include <asm/gpio.h> 14d8de3c73SJagan Teki #include <linux/sizes.h> 15d8de3c73SJagan Teki 16d8de3c73SJagan Teki #include <asm/arch/clock.h> 17d8de3c73SJagan Teki #include <asm/arch/crm_regs.h> 18d8de3c73SJagan Teki #include <asm/arch/iomux.h> 19d8de3c73SJagan Teki #include <asm/arch/mx6-ddr.h> 20d8de3c73SJagan Teki #include <asm/arch/mx6-pins.h> 21d8de3c73SJagan Teki #include <asm/arch/sys_proto.h> 22d8de3c73SJagan Teki 23d8de3c73SJagan Teki #include <asm/imx-common/iomux-v3.h> 24d8de3c73SJagan Teki #include <asm/imx-common/video.h> 25d8de3c73SJagan Teki 26d8de3c73SJagan Teki DECLARE_GLOBAL_DATA_PTR; 27d8de3c73SJagan Teki 28d8de3c73SJagan Teki #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 29d8de3c73SJagan Teki PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 30d8de3c73SJagan Teki PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 31d8de3c73SJagan Teki 32*a81b0fd6SJagan Teki static iomux_v3_cfg_t const uart_pads[] = { 33*a81b0fd6SJagan Teki #ifdef CONFIG_MX6QDL 34d8de3c73SJagan Teki IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 35d8de3c73SJagan Teki IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 36*a81b0fd6SJagan Teki #elif CONFIG_MX6UL 37*a81b0fd6SJagan Teki IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)), 38*a81b0fd6SJagan Teki IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)), 39*a81b0fd6SJagan Teki #endif 40d8de3c73SJagan Teki }; 41d8de3c73SJagan Teki 42*a81b0fd6SJagan Teki #ifdef CONFIG_MX6QDL 43d8de3c73SJagan Teki /* 44d8de3c73SJagan Teki * Driving strength: 45d8de3c73SJagan Teki * 0x30 == 40 Ohm 46d8de3c73SJagan Teki * 0x28 == 48 Ohm 47d8de3c73SJagan Teki */ 48d8de3c73SJagan Teki #define IMX6DQ_DRIVE_STRENGTH 0x30 49d8de3c73SJagan Teki #define IMX6SDL_DRIVE_STRENGTH 0x28 50d8de3c73SJagan Teki 51d8de3c73SJagan Teki /* configure MX6Q/DUAL mmdc DDR io registers */ 52d8de3c73SJagan Teki static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { 53d8de3c73SJagan Teki .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, 54d8de3c73SJagan Teki .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, 55d8de3c73SJagan Teki .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, 56d8de3c73SJagan Teki .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, 57d8de3c73SJagan Teki .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, 58d8de3c73SJagan Teki .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, 59d8de3c73SJagan Teki .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, 60d8de3c73SJagan Teki .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, 61d8de3c73SJagan Teki .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, 62d8de3c73SJagan Teki .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, 63d8de3c73SJagan Teki .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, 64d8de3c73SJagan Teki .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, 65d8de3c73SJagan Teki .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, 66d8de3c73SJagan Teki .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, 67d8de3c73SJagan Teki .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, 68d8de3c73SJagan Teki .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, 69d8de3c73SJagan Teki .dram_cas = IMX6DQ_DRIVE_STRENGTH, 70d8de3c73SJagan Teki .dram_ras = IMX6DQ_DRIVE_STRENGTH, 71d8de3c73SJagan Teki .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, 72d8de3c73SJagan Teki .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, 73d8de3c73SJagan Teki .dram_reset = IMX6DQ_DRIVE_STRENGTH, 74d8de3c73SJagan Teki .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH, 75d8de3c73SJagan Teki .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH, 76d8de3c73SJagan Teki .dram_sdba2 = 0x00000000, 77d8de3c73SJagan Teki .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, 78d8de3c73SJagan Teki .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, 79d8de3c73SJagan Teki }; 80d8de3c73SJagan Teki 81d8de3c73SJagan Teki /* configure MX6Q/DUAL mmdc GRP io registers */ 82d8de3c73SJagan Teki static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { 83d8de3c73SJagan Teki .grp_b0ds = IMX6DQ_DRIVE_STRENGTH, 84d8de3c73SJagan Teki .grp_b1ds = IMX6DQ_DRIVE_STRENGTH, 85d8de3c73SJagan Teki .grp_b2ds = IMX6DQ_DRIVE_STRENGTH, 86d8de3c73SJagan Teki .grp_b3ds = IMX6DQ_DRIVE_STRENGTH, 87d8de3c73SJagan Teki .grp_b4ds = IMX6DQ_DRIVE_STRENGTH, 88d8de3c73SJagan Teki .grp_b5ds = IMX6DQ_DRIVE_STRENGTH, 89d8de3c73SJagan Teki .grp_b6ds = IMX6DQ_DRIVE_STRENGTH, 90d8de3c73SJagan Teki .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, 91d8de3c73SJagan Teki .grp_addds = IMX6DQ_DRIVE_STRENGTH, 92d8de3c73SJagan Teki .grp_ddrmode_ctl = 0x00020000, 93d8de3c73SJagan Teki .grp_ddrpke = 0x00000000, 94d8de3c73SJagan Teki .grp_ddrmode = 0x00020000, 95d8de3c73SJagan Teki .grp_ctlds = IMX6DQ_DRIVE_STRENGTH, 96d8de3c73SJagan Teki .grp_ddr_type = 0x000c0000, 97d8de3c73SJagan Teki }; 98d8de3c73SJagan Teki 99d8de3c73SJagan Teki /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ 100d8de3c73SJagan Teki struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { 101d8de3c73SJagan Teki .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, 102d8de3c73SJagan Teki .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, 103d8de3c73SJagan Teki .dram_cas = IMX6SDL_DRIVE_STRENGTH, 104d8de3c73SJagan Teki .dram_ras = IMX6SDL_DRIVE_STRENGTH, 105d8de3c73SJagan Teki .dram_reset = IMX6SDL_DRIVE_STRENGTH, 106d8de3c73SJagan Teki .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, 107d8de3c73SJagan Teki .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, 108d8de3c73SJagan Teki .dram_sdba2 = 0x00000000, 109d8de3c73SJagan Teki .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, 110d8de3c73SJagan Teki .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, 111d8de3c73SJagan Teki .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, 112d8de3c73SJagan Teki .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, 113d8de3c73SJagan Teki .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, 114d8de3c73SJagan Teki .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, 115d8de3c73SJagan Teki .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, 116d8de3c73SJagan Teki .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, 117d8de3c73SJagan Teki .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, 118d8de3c73SJagan Teki .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, 119d8de3c73SJagan Teki .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, 120d8de3c73SJagan Teki .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, 121d8de3c73SJagan Teki .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, 122d8de3c73SJagan Teki .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, 123d8de3c73SJagan Teki .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, 124d8de3c73SJagan Teki .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, 125d8de3c73SJagan Teki .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, 126d8de3c73SJagan Teki .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, 127d8de3c73SJagan Teki }; 128d8de3c73SJagan Teki 129d8de3c73SJagan Teki /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ 130d8de3c73SJagan Teki struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { 131d8de3c73SJagan Teki .grp_ddr_type = 0x000c0000, 132d8de3c73SJagan Teki .grp_ddrmode_ctl = 0x00020000, 133d8de3c73SJagan Teki .grp_ddrpke = 0x00000000, 134d8de3c73SJagan Teki .grp_addds = IMX6SDL_DRIVE_STRENGTH, 135d8de3c73SJagan Teki .grp_ctlds = IMX6SDL_DRIVE_STRENGTH, 136d8de3c73SJagan Teki .grp_ddrmode = 0x00020000, 137d8de3c73SJagan Teki .grp_b0ds = IMX6SDL_DRIVE_STRENGTH, 138d8de3c73SJagan Teki .grp_b1ds = IMX6SDL_DRIVE_STRENGTH, 139d8de3c73SJagan Teki .grp_b2ds = IMX6SDL_DRIVE_STRENGTH, 140d8de3c73SJagan Teki .grp_b3ds = IMX6SDL_DRIVE_STRENGTH, 141d8de3c73SJagan Teki .grp_b4ds = IMX6SDL_DRIVE_STRENGTH, 142d8de3c73SJagan Teki .grp_b5ds = IMX6SDL_DRIVE_STRENGTH, 143d8de3c73SJagan Teki .grp_b6ds = IMX6SDL_DRIVE_STRENGTH, 144d8de3c73SJagan Teki .grp_b7ds = IMX6SDL_DRIVE_STRENGTH, 145d8de3c73SJagan Teki }; 146d8de3c73SJagan Teki 147d8de3c73SJagan Teki /* mt41j256 */ 148d8de3c73SJagan Teki static struct mx6_ddr3_cfg mt41j256 = { 149d8de3c73SJagan Teki .mem_speed = 1066, 150d8de3c73SJagan Teki .density = 2, 151d8de3c73SJagan Teki .width = 16, 152d8de3c73SJagan Teki .banks = 8, 153d8de3c73SJagan Teki .rowaddr = 13, 154d8de3c73SJagan Teki .coladdr = 10, 155d8de3c73SJagan Teki .pagesz = 2, 156d8de3c73SJagan Teki .trcd = 1375, 157d8de3c73SJagan Teki .trcmin = 4875, 158d8de3c73SJagan Teki .trasmin = 3500, 159d8de3c73SJagan Teki .SRT = 0, 160d8de3c73SJagan Teki }; 161d8de3c73SJagan Teki 162d8de3c73SJagan Teki static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { 163d8de3c73SJagan Teki .p0_mpwldectrl0 = 0x000E0009, 164d8de3c73SJagan Teki .p0_mpwldectrl1 = 0x0018000E, 165d8de3c73SJagan Teki .p1_mpwldectrl0 = 0x00000007, 166d8de3c73SJagan Teki .p1_mpwldectrl1 = 0x00000000, 167d8de3c73SJagan Teki .p0_mpdgctrl0 = 0x43280334, 168d8de3c73SJagan Teki .p0_mpdgctrl1 = 0x031C0314, 169d8de3c73SJagan Teki .p1_mpdgctrl0 = 0x4318031C, 170d8de3c73SJagan Teki .p1_mpdgctrl1 = 0x030C0258, 171d8de3c73SJagan Teki .p0_mprddlctl = 0x3E343A40, 172d8de3c73SJagan Teki .p1_mprddlctl = 0x383C3844, 173d8de3c73SJagan Teki .p0_mpwrdlctl = 0x40404440, 174d8de3c73SJagan Teki .p1_mpwrdlctl = 0x4C3E4446, 175d8de3c73SJagan Teki }; 176d8de3c73SJagan Teki 177d8de3c73SJagan Teki /* DDR 64bit */ 178d8de3c73SJagan Teki static struct mx6_ddr_sysinfo mem_q = { 179d8de3c73SJagan Teki .ddr_type = DDR_TYPE_DDR3, 180d8de3c73SJagan Teki .dsize = 2, 181d8de3c73SJagan Teki .cs1_mirror = 0, 182d8de3c73SJagan Teki /* config for full 4GB range so that get_mem_size() works */ 183d8de3c73SJagan Teki .cs_density = 32, 184d8de3c73SJagan Teki .ncs = 1, 185d8de3c73SJagan Teki .bi_on = 1, 186d8de3c73SJagan Teki .rtt_nom = 2, 187d8de3c73SJagan Teki .rtt_wr = 2, 188d8de3c73SJagan Teki .ralat = 5, 189d8de3c73SJagan Teki .walat = 0, 190d8de3c73SJagan Teki .mif3_mode = 3, 191d8de3c73SJagan Teki .rst_to_cke = 0x23, 192d8de3c73SJagan Teki .sde_to_rst = 0x10, 193d8de3c73SJagan Teki }; 194d8de3c73SJagan Teki 195d8de3c73SJagan Teki static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { 196d8de3c73SJagan Teki .p0_mpwldectrl0 = 0x001F0024, 197d8de3c73SJagan Teki .p0_mpwldectrl1 = 0x00110018, 198d8de3c73SJagan Teki .p1_mpwldectrl0 = 0x001F0024, 199d8de3c73SJagan Teki .p1_mpwldectrl1 = 0x00110018, 200d8de3c73SJagan Teki .p0_mpdgctrl0 = 0x4230022C, 201d8de3c73SJagan Teki .p0_mpdgctrl1 = 0x02180220, 202d8de3c73SJagan Teki .p1_mpdgctrl0 = 0x42440248, 203d8de3c73SJagan Teki .p1_mpdgctrl1 = 0x02300238, 204d8de3c73SJagan Teki .p0_mprddlctl = 0x44444A48, 205d8de3c73SJagan Teki .p1_mprddlctl = 0x46484A42, 206d8de3c73SJagan Teki .p0_mpwrdlctl = 0x38383234, 207d8de3c73SJagan Teki .p1_mpwrdlctl = 0x3C34362E, 208d8de3c73SJagan Teki }; 209d8de3c73SJagan Teki 210d8de3c73SJagan Teki /* DDR 64bit 1GB */ 211d8de3c73SJagan Teki static struct mx6_ddr_sysinfo mem_dl = { 212d8de3c73SJagan Teki .dsize = 2, 213d8de3c73SJagan Teki .cs1_mirror = 0, 214d8de3c73SJagan Teki /* config for full 4GB range so that get_mem_size() works */ 215d8de3c73SJagan Teki .cs_density = 32, 216d8de3c73SJagan Teki .ncs = 1, 217d8de3c73SJagan Teki .bi_on = 1, 218d8de3c73SJagan Teki .rtt_nom = 1, 219d8de3c73SJagan Teki .rtt_wr = 1, 220d8de3c73SJagan Teki .ralat = 5, 221d8de3c73SJagan Teki .walat = 0, 222d8de3c73SJagan Teki .mif3_mode = 3, 223d8de3c73SJagan Teki .rst_to_cke = 0x23, 224d8de3c73SJagan Teki .sde_to_rst = 0x10, 225d8de3c73SJagan Teki }; 226d8de3c73SJagan Teki 227d8de3c73SJagan Teki /* DDR 32bit 512MB */ 228d8de3c73SJagan Teki static struct mx6_ddr_sysinfo mem_s = { 229d8de3c73SJagan Teki .dsize = 1, 230d8de3c73SJagan Teki .cs1_mirror = 0, 231d8de3c73SJagan Teki /* config for full 4GB range so that get_mem_size() works */ 232d8de3c73SJagan Teki .cs_density = 32, 233d8de3c73SJagan Teki .ncs = 1, 234d8de3c73SJagan Teki .bi_on = 1, 235d8de3c73SJagan Teki .rtt_nom = 1, 236d8de3c73SJagan Teki .rtt_wr = 1, 237d8de3c73SJagan Teki .ralat = 5, 238d8de3c73SJagan Teki .walat = 0, 239d8de3c73SJagan Teki .mif3_mode = 3, 240d8de3c73SJagan Teki .rst_to_cke = 0x23, 241d8de3c73SJagan Teki .sde_to_rst = 0x10, 242d8de3c73SJagan Teki }; 243*a81b0fd6SJagan Teki #endif /* CONFIG_MX6QDL */ 244*a81b0fd6SJagan Teki 245*a81b0fd6SJagan Teki #ifdef CONFIG_MX6UL 246*a81b0fd6SJagan Teki static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { 247*a81b0fd6SJagan Teki .grp_addds = 0x00000030, 248*a81b0fd6SJagan Teki .grp_ddrmode_ctl = 0x00020000, 249*a81b0fd6SJagan Teki .grp_b0ds = 0x00000030, 250*a81b0fd6SJagan Teki .grp_ctlds = 0x00000030, 251*a81b0fd6SJagan Teki .grp_b1ds = 0x00000030, 252*a81b0fd6SJagan Teki .grp_ddrpke = 0x00000000, 253*a81b0fd6SJagan Teki .grp_ddrmode = 0x00020000, 254*a81b0fd6SJagan Teki .grp_ddr_type = 0x000c0000, 255*a81b0fd6SJagan Teki }; 256*a81b0fd6SJagan Teki 257*a81b0fd6SJagan Teki static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 258*a81b0fd6SJagan Teki .dram_dqm0 = 0x00000030, 259*a81b0fd6SJagan Teki .dram_dqm1 = 0x00000030, 260*a81b0fd6SJagan Teki .dram_ras = 0x00000030, 261*a81b0fd6SJagan Teki .dram_cas = 0x00000030, 262*a81b0fd6SJagan Teki .dram_odt0 = 0x00000030, 263*a81b0fd6SJagan Teki .dram_odt1 = 0x00000030, 264*a81b0fd6SJagan Teki .dram_sdba2 = 0x00000000, 265*a81b0fd6SJagan Teki .dram_sdclk_0 = 0x00000008, 266*a81b0fd6SJagan Teki .dram_sdqs0 = 0x00000038, 267*a81b0fd6SJagan Teki .dram_sdqs1 = 0x00000030, 268*a81b0fd6SJagan Teki .dram_reset = 0x00000030, 269*a81b0fd6SJagan Teki }; 270*a81b0fd6SJagan Teki 271*a81b0fd6SJagan Teki static struct mx6_mmdc_calibration mx6_mmcd_calib = { 272*a81b0fd6SJagan Teki .p0_mpwldectrl0 = 0x00070007, 273*a81b0fd6SJagan Teki .p0_mpdgctrl0 = 0x41490145, 274*a81b0fd6SJagan Teki .p0_mprddlctl = 0x40404546, 275*a81b0fd6SJagan Teki .p0_mpwrdlctl = 0x4040524D, 276*a81b0fd6SJagan Teki }; 277*a81b0fd6SJagan Teki 278*a81b0fd6SJagan Teki struct mx6_ddr_sysinfo ddr_sysinfo = { 279*a81b0fd6SJagan Teki .dsize = 0, 280*a81b0fd6SJagan Teki .cs_density = 20, 281*a81b0fd6SJagan Teki .ncs = 1, 282*a81b0fd6SJagan Teki .cs1_mirror = 0, 283*a81b0fd6SJagan Teki .rtt_wr = 2, 284*a81b0fd6SJagan Teki .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 285*a81b0fd6SJagan Teki .walat = 1, /* Write additional latency */ 286*a81b0fd6SJagan Teki .ralat = 5, /* Read additional latency */ 287*a81b0fd6SJagan Teki .mif3_mode = 3, /* Command prediction working mode */ 288*a81b0fd6SJagan Teki .bi_on = 1, /* Bank interleaving enabled */ 289*a81b0fd6SJagan Teki .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 290*a81b0fd6SJagan Teki .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 291*a81b0fd6SJagan Teki .ddr_type = DDR_TYPE_DDR3, 292*a81b0fd6SJagan Teki }; 293*a81b0fd6SJagan Teki 294*a81b0fd6SJagan Teki static struct mx6_ddr3_cfg mem_ddr = { 295*a81b0fd6SJagan Teki .mem_speed = 800, 296*a81b0fd6SJagan Teki .density = 4, 297*a81b0fd6SJagan Teki .width = 16, 298*a81b0fd6SJagan Teki .banks = 8, 299*a81b0fd6SJagan Teki #ifdef TARGET_MX6UL_ISIOT 300*a81b0fd6SJagan Teki .rowaddr = 15, 301*a81b0fd6SJagan Teki #else 302*a81b0fd6SJagan Teki .rowaddr = 13, 303*a81b0fd6SJagan Teki #endif 304*a81b0fd6SJagan Teki .coladdr = 10, 305*a81b0fd6SJagan Teki .pagesz = 2, 306*a81b0fd6SJagan Teki .trcd = 1375, 307*a81b0fd6SJagan Teki .trcmin = 4875, 308*a81b0fd6SJagan Teki .trasmin = 3500, 309*a81b0fd6SJagan Teki }; 310*a81b0fd6SJagan Teki #endif /* CONFIG_MX6UL */ 311d8de3c73SJagan Teki 312d8de3c73SJagan Teki static void ccgr_init(void) 313d8de3c73SJagan Teki { 314d8de3c73SJagan Teki struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 315d8de3c73SJagan Teki 316*a81b0fd6SJagan Teki #ifdef CONFIG_MX6QDL 317d8de3c73SJagan Teki writel(0x00003F3F, &ccm->CCGR0); 318d8de3c73SJagan Teki writel(0x0030FC00, &ccm->CCGR1); 319d8de3c73SJagan Teki writel(0x000FC000, &ccm->CCGR2); 320d8de3c73SJagan Teki writel(0x3F300000, &ccm->CCGR3); 321d8de3c73SJagan Teki writel(0xFF00F300, &ccm->CCGR4); 322d8de3c73SJagan Teki writel(0x0F0000C3, &ccm->CCGR5); 323d8de3c73SJagan Teki writel(0x000003CC, &ccm->CCGR6); 324*a81b0fd6SJagan Teki #elif CONFIG_MX6UL 325*a81b0fd6SJagan Teki writel(0x00c03f3f, &ccm->CCGR0); 326*a81b0fd6SJagan Teki writel(0xfcffff00, &ccm->CCGR1); 327*a81b0fd6SJagan Teki writel(0x0cffffcc, &ccm->CCGR2); 328*a81b0fd6SJagan Teki writel(0x3f3c3030, &ccm->CCGR3); 329*a81b0fd6SJagan Teki writel(0xff00fffc, &ccm->CCGR4); 330*a81b0fd6SJagan Teki writel(0x033f30ff, &ccm->CCGR5); 331*a81b0fd6SJagan Teki writel(0x00c00fff, &ccm->CCGR6); 332*a81b0fd6SJagan Teki #endif 333d8de3c73SJagan Teki } 334d8de3c73SJagan Teki 335d8de3c73SJagan Teki static void gpr_init(void) 336d8de3c73SJagan Teki { 337d8de3c73SJagan Teki struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 338d8de3c73SJagan Teki 339d8de3c73SJagan Teki /* enable AXI cache for VDOA/VPU/IPU */ 340d8de3c73SJagan Teki writel(0xF00000CF, &iomux->gpr[4]); 341d8de3c73SJagan Teki /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 342d8de3c73SJagan Teki writel(0x007F007F, &iomux->gpr[6]); 343d8de3c73SJagan Teki writel(0x007F007F, &iomux->gpr[7]); 344d8de3c73SJagan Teki } 345d8de3c73SJagan Teki 346d8de3c73SJagan Teki static void spl_dram_init(void) 347d8de3c73SJagan Teki { 348*a81b0fd6SJagan Teki #ifdef CONFIG_MX6QDL 349d8de3c73SJagan Teki if (is_mx6solo()) { 350d8de3c73SJagan Teki mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 351d8de3c73SJagan Teki mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); 352d8de3c73SJagan Teki } else if (is_mx6dl()) { 353d8de3c73SJagan Teki mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 354d8de3c73SJagan Teki mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); 355d8de3c73SJagan Teki } else if (is_mx6dq()) { 356d8de3c73SJagan Teki mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); 357d8de3c73SJagan Teki mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); 358d8de3c73SJagan Teki } 359*a81b0fd6SJagan Teki #elif CONFIG_MX6UL 360*a81b0fd6SJagan Teki mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 361*a81b0fd6SJagan Teki mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); 362*a81b0fd6SJagan Teki #endif 363d8de3c73SJagan Teki 364d8de3c73SJagan Teki udelay(100); 365d8de3c73SJagan Teki } 366d8de3c73SJagan Teki 367d8de3c73SJagan Teki void board_init_f(ulong dummy) 368d8de3c73SJagan Teki { 369d8de3c73SJagan Teki ccgr_init(); 370d8de3c73SJagan Teki 371d8de3c73SJagan Teki /* setup AIPS and disable watchdog */ 372d8de3c73SJagan Teki arch_cpu_init(); 373d8de3c73SJagan Teki 374d8de3c73SJagan Teki gpr_init(); 375d8de3c73SJagan Teki 376d8de3c73SJagan Teki /* iomux */ 377*a81b0fd6SJagan Teki SETUP_IOMUX_PADS(uart_pads); 378d8de3c73SJagan Teki 379d8de3c73SJagan Teki /* setup GP timer */ 380d8de3c73SJagan Teki timer_init(); 381d8de3c73SJagan Teki 382d8de3c73SJagan Teki /* UART clocks enabled and gd valid - init serial console */ 383d8de3c73SJagan Teki preloader_console_init(); 384d8de3c73SJagan Teki 385d8de3c73SJagan Teki /* DDR initialization */ 386d8de3c73SJagan Teki spl_dram_init(); 387d8de3c73SJagan Teki 388d8de3c73SJagan Teki /* Clear the BSS. */ 389d8de3c73SJagan Teki memset(__bss_start, 0, __bss_end - __bss_start); 390d8de3c73SJagan Teki 391d8de3c73SJagan Teki /* load/boot image from boot device */ 392d8de3c73SJagan Teki board_init_r(NULL, 0); 393d8de3c73SJagan Teki } 394