1d8de3c73SJagan Teki /* 2d8de3c73SJagan Teki * Copyright (C) 2016 Amarula Solutions B.V. 3d8de3c73SJagan Teki * Copyright (C) 2016 Engicam S.r.l. 4d8de3c73SJagan Teki * Author: Jagan Teki <jagan@amarulasolutions.com> 5d8de3c73SJagan Teki * 6d8de3c73SJagan Teki * SPDX-License-Identifier: GPL-2.0+ 7d8de3c73SJagan Teki */ 8d8de3c73SJagan Teki 9d8de3c73SJagan Teki #include <common.h> 10d8de3c73SJagan Teki #include <spl.h> 11d8de3c73SJagan Teki 12d8de3c73SJagan Teki #include <asm/io.h> 13d8de3c73SJagan Teki #include <asm/gpio.h> 14d8de3c73SJagan Teki #include <linux/sizes.h> 15d8de3c73SJagan Teki 16d8de3c73SJagan Teki #include <asm/arch/clock.h> 17d8de3c73SJagan Teki #include <asm/arch/crm_regs.h> 18d8de3c73SJagan Teki #include <asm/arch/iomux.h> 19d8de3c73SJagan Teki #include <asm/arch/mx6-ddr.h> 20d8de3c73SJagan Teki #include <asm/arch/mx6-pins.h> 21d8de3c73SJagan Teki #include <asm/arch/sys_proto.h> 22d8de3c73SJagan Teki 23552a848eSStefano Babic #include <asm/mach-imx/iomux-v3.h> 24552a848eSStefano Babic #include <asm/mach-imx/video.h> 25d8de3c73SJagan Teki 26d8de3c73SJagan Teki DECLARE_GLOBAL_DATA_PTR; 27d8de3c73SJagan Teki 28d8de3c73SJagan Teki #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 29d8de3c73SJagan Teki PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 30d8de3c73SJagan Teki PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 31d8de3c73SJagan Teki 32a81b0fd6SJagan Teki static iomux_v3_cfg_t const uart_pads[] = { 33a81b0fd6SJagan Teki #ifdef CONFIG_MX6QDL 34d8de3c73SJagan Teki IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 35d8de3c73SJagan Teki IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 36a81b0fd6SJagan Teki #elif CONFIG_MX6UL 37a81b0fd6SJagan Teki IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)), 38a81b0fd6SJagan Teki IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)), 39a81b0fd6SJagan Teki #endif 40d8de3c73SJagan Teki }; 41d8de3c73SJagan Teki 42*63af4b0aSJagan Teki #ifdef CONFIG_SPL_OS_BOOT 43*63af4b0aSJagan Teki int spl_start_uboot(void) 44*63af4b0aSJagan Teki { 45*63af4b0aSJagan Teki /* break into full u-boot on 'c' */ 46*63af4b0aSJagan Teki if (serial_tstc() && serial_getc() == 'c') 47*63af4b0aSJagan Teki return 1; 48*63af4b0aSJagan Teki 49*63af4b0aSJagan Teki return 0; 50*63af4b0aSJagan Teki } 51*63af4b0aSJagan Teki #endif 52*63af4b0aSJagan Teki 53a81b0fd6SJagan Teki #ifdef CONFIG_MX6QDL 54d8de3c73SJagan Teki /* 55d8de3c73SJagan Teki * Driving strength: 56d8de3c73SJagan Teki * 0x30 == 40 Ohm 57d8de3c73SJagan Teki * 0x28 == 48 Ohm 58d8de3c73SJagan Teki */ 59d8de3c73SJagan Teki #define IMX6DQ_DRIVE_STRENGTH 0x30 60d8de3c73SJagan Teki #define IMX6SDL_DRIVE_STRENGTH 0x28 61d8de3c73SJagan Teki 62d8de3c73SJagan Teki /* configure MX6Q/DUAL mmdc DDR io registers */ 63d8de3c73SJagan Teki static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { 64d8de3c73SJagan Teki .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, 65d8de3c73SJagan Teki .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, 66d8de3c73SJagan Teki .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, 67d8de3c73SJagan Teki .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, 68d8de3c73SJagan Teki .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, 69d8de3c73SJagan Teki .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, 70d8de3c73SJagan Teki .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, 71d8de3c73SJagan Teki .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, 72d8de3c73SJagan Teki .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, 73d8de3c73SJagan Teki .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, 74d8de3c73SJagan Teki .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, 75d8de3c73SJagan Teki .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, 76d8de3c73SJagan Teki .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, 77d8de3c73SJagan Teki .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, 78d8de3c73SJagan Teki .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, 79d8de3c73SJagan Teki .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, 80d8de3c73SJagan Teki .dram_cas = IMX6DQ_DRIVE_STRENGTH, 81d8de3c73SJagan Teki .dram_ras = IMX6DQ_DRIVE_STRENGTH, 82d8de3c73SJagan Teki .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, 83d8de3c73SJagan Teki .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, 84d8de3c73SJagan Teki .dram_reset = IMX6DQ_DRIVE_STRENGTH, 85d8de3c73SJagan Teki .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH, 86d8de3c73SJagan Teki .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH, 87d8de3c73SJagan Teki .dram_sdba2 = 0x00000000, 88d8de3c73SJagan Teki .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, 89d8de3c73SJagan Teki .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, 90d8de3c73SJagan Teki }; 91d8de3c73SJagan Teki 92d8de3c73SJagan Teki /* configure MX6Q/DUAL mmdc GRP io registers */ 93d8de3c73SJagan Teki static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { 94d8de3c73SJagan Teki .grp_b0ds = IMX6DQ_DRIVE_STRENGTH, 95d8de3c73SJagan Teki .grp_b1ds = IMX6DQ_DRIVE_STRENGTH, 96d8de3c73SJagan Teki .grp_b2ds = IMX6DQ_DRIVE_STRENGTH, 97d8de3c73SJagan Teki .grp_b3ds = IMX6DQ_DRIVE_STRENGTH, 98d8de3c73SJagan Teki .grp_b4ds = IMX6DQ_DRIVE_STRENGTH, 99d8de3c73SJagan Teki .grp_b5ds = IMX6DQ_DRIVE_STRENGTH, 100d8de3c73SJagan Teki .grp_b6ds = IMX6DQ_DRIVE_STRENGTH, 101d8de3c73SJagan Teki .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, 102d8de3c73SJagan Teki .grp_addds = IMX6DQ_DRIVE_STRENGTH, 103d8de3c73SJagan Teki .grp_ddrmode_ctl = 0x00020000, 104d8de3c73SJagan Teki .grp_ddrpke = 0x00000000, 105d8de3c73SJagan Teki .grp_ddrmode = 0x00020000, 106d8de3c73SJagan Teki .grp_ctlds = IMX6DQ_DRIVE_STRENGTH, 107d8de3c73SJagan Teki .grp_ddr_type = 0x000c0000, 108d8de3c73SJagan Teki }; 109d8de3c73SJagan Teki 110d8de3c73SJagan Teki /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ 111d8de3c73SJagan Teki struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { 112d8de3c73SJagan Teki .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, 113d8de3c73SJagan Teki .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, 114d8de3c73SJagan Teki .dram_cas = IMX6SDL_DRIVE_STRENGTH, 115d8de3c73SJagan Teki .dram_ras = IMX6SDL_DRIVE_STRENGTH, 116d8de3c73SJagan Teki .dram_reset = IMX6SDL_DRIVE_STRENGTH, 117d8de3c73SJagan Teki .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, 118d8de3c73SJagan Teki .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, 119d8de3c73SJagan Teki .dram_sdba2 = 0x00000000, 120d8de3c73SJagan Teki .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, 121d8de3c73SJagan Teki .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, 122d8de3c73SJagan Teki .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, 123d8de3c73SJagan Teki .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, 124d8de3c73SJagan Teki .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, 125d8de3c73SJagan Teki .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, 126d8de3c73SJagan Teki .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, 127d8de3c73SJagan Teki .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, 128d8de3c73SJagan Teki .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, 129d8de3c73SJagan Teki .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, 130d8de3c73SJagan Teki .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, 131d8de3c73SJagan Teki .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, 132d8de3c73SJagan Teki .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, 133d8de3c73SJagan Teki .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, 134d8de3c73SJagan Teki .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, 135d8de3c73SJagan Teki .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, 136d8de3c73SJagan Teki .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, 137d8de3c73SJagan Teki .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, 138d8de3c73SJagan Teki }; 139d8de3c73SJagan Teki 140d8de3c73SJagan Teki /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ 141d8de3c73SJagan Teki struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { 142d8de3c73SJagan Teki .grp_ddr_type = 0x000c0000, 143d8de3c73SJagan Teki .grp_ddrmode_ctl = 0x00020000, 144d8de3c73SJagan Teki .grp_ddrpke = 0x00000000, 145d8de3c73SJagan Teki .grp_addds = IMX6SDL_DRIVE_STRENGTH, 146d8de3c73SJagan Teki .grp_ctlds = IMX6SDL_DRIVE_STRENGTH, 147d8de3c73SJagan Teki .grp_ddrmode = 0x00020000, 148d8de3c73SJagan Teki .grp_b0ds = IMX6SDL_DRIVE_STRENGTH, 149d8de3c73SJagan Teki .grp_b1ds = IMX6SDL_DRIVE_STRENGTH, 150d8de3c73SJagan Teki .grp_b2ds = IMX6SDL_DRIVE_STRENGTH, 151d8de3c73SJagan Teki .grp_b3ds = IMX6SDL_DRIVE_STRENGTH, 152d8de3c73SJagan Teki .grp_b4ds = IMX6SDL_DRIVE_STRENGTH, 153d8de3c73SJagan Teki .grp_b5ds = IMX6SDL_DRIVE_STRENGTH, 154d8de3c73SJagan Teki .grp_b6ds = IMX6SDL_DRIVE_STRENGTH, 155d8de3c73SJagan Teki .grp_b7ds = IMX6SDL_DRIVE_STRENGTH, 156d8de3c73SJagan Teki }; 157d8de3c73SJagan Teki 158d8de3c73SJagan Teki /* mt41j256 */ 159d8de3c73SJagan Teki static struct mx6_ddr3_cfg mt41j256 = { 160d8de3c73SJagan Teki .mem_speed = 1066, 161d8de3c73SJagan Teki .density = 2, 162d8de3c73SJagan Teki .width = 16, 163d8de3c73SJagan Teki .banks = 8, 164d8de3c73SJagan Teki .rowaddr = 13, 165d8de3c73SJagan Teki .coladdr = 10, 166d8de3c73SJagan Teki .pagesz = 2, 167d8de3c73SJagan Teki .trcd = 1375, 168d8de3c73SJagan Teki .trcmin = 4875, 169d8de3c73SJagan Teki .trasmin = 3500, 170d8de3c73SJagan Teki .SRT = 0, 171d8de3c73SJagan Teki }; 172d8de3c73SJagan Teki 173d8de3c73SJagan Teki static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { 174d8de3c73SJagan Teki .p0_mpwldectrl0 = 0x000E0009, 175d8de3c73SJagan Teki .p0_mpwldectrl1 = 0x0018000E, 176d8de3c73SJagan Teki .p1_mpwldectrl0 = 0x00000007, 177d8de3c73SJagan Teki .p1_mpwldectrl1 = 0x00000000, 178d8de3c73SJagan Teki .p0_mpdgctrl0 = 0x43280334, 179d8de3c73SJagan Teki .p0_mpdgctrl1 = 0x031C0314, 180d8de3c73SJagan Teki .p1_mpdgctrl0 = 0x4318031C, 181d8de3c73SJagan Teki .p1_mpdgctrl1 = 0x030C0258, 182d8de3c73SJagan Teki .p0_mprddlctl = 0x3E343A40, 183d8de3c73SJagan Teki .p1_mprddlctl = 0x383C3844, 184d8de3c73SJagan Teki .p0_mpwrdlctl = 0x40404440, 185d8de3c73SJagan Teki .p1_mpwrdlctl = 0x4C3E4446, 186d8de3c73SJagan Teki }; 187d8de3c73SJagan Teki 188d8de3c73SJagan Teki /* DDR 64bit */ 189d8de3c73SJagan Teki static struct mx6_ddr_sysinfo mem_q = { 190d8de3c73SJagan Teki .ddr_type = DDR_TYPE_DDR3, 191d8de3c73SJagan Teki .dsize = 2, 192d8de3c73SJagan Teki .cs1_mirror = 0, 193d8de3c73SJagan Teki /* config for full 4GB range so that get_mem_size() works */ 194d8de3c73SJagan Teki .cs_density = 32, 195d8de3c73SJagan Teki .ncs = 1, 196d8de3c73SJagan Teki .bi_on = 1, 197d8de3c73SJagan Teki .rtt_nom = 2, 198d8de3c73SJagan Teki .rtt_wr = 2, 199d8de3c73SJagan Teki .ralat = 5, 200d8de3c73SJagan Teki .walat = 0, 201d8de3c73SJagan Teki .mif3_mode = 3, 202d8de3c73SJagan Teki .rst_to_cke = 0x23, 203d8de3c73SJagan Teki .sde_to_rst = 0x10, 204d8de3c73SJagan Teki }; 205d8de3c73SJagan Teki 206d8de3c73SJagan Teki static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { 207d8de3c73SJagan Teki .p0_mpwldectrl0 = 0x001F0024, 208d8de3c73SJagan Teki .p0_mpwldectrl1 = 0x00110018, 209d8de3c73SJagan Teki .p1_mpwldectrl0 = 0x001F0024, 210d8de3c73SJagan Teki .p1_mpwldectrl1 = 0x00110018, 211d8de3c73SJagan Teki .p0_mpdgctrl0 = 0x4230022C, 212d8de3c73SJagan Teki .p0_mpdgctrl1 = 0x02180220, 213d8de3c73SJagan Teki .p1_mpdgctrl0 = 0x42440248, 214d8de3c73SJagan Teki .p1_mpdgctrl1 = 0x02300238, 215d8de3c73SJagan Teki .p0_mprddlctl = 0x44444A48, 216d8de3c73SJagan Teki .p1_mprddlctl = 0x46484A42, 217d8de3c73SJagan Teki .p0_mpwrdlctl = 0x38383234, 218d8de3c73SJagan Teki .p1_mpwrdlctl = 0x3C34362E, 219d8de3c73SJagan Teki }; 220d8de3c73SJagan Teki 221d8de3c73SJagan Teki /* DDR 64bit 1GB */ 222d8de3c73SJagan Teki static struct mx6_ddr_sysinfo mem_dl = { 223d8de3c73SJagan Teki .dsize = 2, 224d8de3c73SJagan Teki .cs1_mirror = 0, 225d8de3c73SJagan Teki /* config for full 4GB range so that get_mem_size() works */ 226d8de3c73SJagan Teki .cs_density = 32, 227d8de3c73SJagan Teki .ncs = 1, 228d8de3c73SJagan Teki .bi_on = 1, 229d8de3c73SJagan Teki .rtt_nom = 1, 230d8de3c73SJagan Teki .rtt_wr = 1, 231d8de3c73SJagan Teki .ralat = 5, 232d8de3c73SJagan Teki .walat = 0, 233d8de3c73SJagan Teki .mif3_mode = 3, 234d8de3c73SJagan Teki .rst_to_cke = 0x23, 235d8de3c73SJagan Teki .sde_to_rst = 0x10, 236d8de3c73SJagan Teki }; 237d8de3c73SJagan Teki 238d8de3c73SJagan Teki /* DDR 32bit 512MB */ 239d8de3c73SJagan Teki static struct mx6_ddr_sysinfo mem_s = { 240d8de3c73SJagan Teki .dsize = 1, 241d8de3c73SJagan Teki .cs1_mirror = 0, 242d8de3c73SJagan Teki /* config for full 4GB range so that get_mem_size() works */ 243d8de3c73SJagan Teki .cs_density = 32, 244d8de3c73SJagan Teki .ncs = 1, 245d8de3c73SJagan Teki .bi_on = 1, 246d8de3c73SJagan Teki .rtt_nom = 1, 247d8de3c73SJagan Teki .rtt_wr = 1, 248d8de3c73SJagan Teki .ralat = 5, 249d8de3c73SJagan Teki .walat = 0, 250d8de3c73SJagan Teki .mif3_mode = 3, 251d8de3c73SJagan Teki .rst_to_cke = 0x23, 252d8de3c73SJagan Teki .sde_to_rst = 0x10, 253d8de3c73SJagan Teki }; 254a81b0fd6SJagan Teki #endif /* CONFIG_MX6QDL */ 255a81b0fd6SJagan Teki 256a81b0fd6SJagan Teki #ifdef CONFIG_MX6UL 257a81b0fd6SJagan Teki static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { 258a81b0fd6SJagan Teki .grp_addds = 0x00000030, 259a81b0fd6SJagan Teki .grp_ddrmode_ctl = 0x00020000, 260a81b0fd6SJagan Teki .grp_b0ds = 0x00000030, 261a81b0fd6SJagan Teki .grp_ctlds = 0x00000030, 262a81b0fd6SJagan Teki .grp_b1ds = 0x00000030, 263a81b0fd6SJagan Teki .grp_ddrpke = 0x00000000, 264a81b0fd6SJagan Teki .grp_ddrmode = 0x00020000, 265a81b0fd6SJagan Teki .grp_ddr_type = 0x000c0000, 266a81b0fd6SJagan Teki }; 267a81b0fd6SJagan Teki 268a81b0fd6SJagan Teki static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 269a81b0fd6SJagan Teki .dram_dqm0 = 0x00000030, 270a81b0fd6SJagan Teki .dram_dqm1 = 0x00000030, 271a81b0fd6SJagan Teki .dram_ras = 0x00000030, 272a81b0fd6SJagan Teki .dram_cas = 0x00000030, 273a81b0fd6SJagan Teki .dram_odt0 = 0x00000030, 274a81b0fd6SJagan Teki .dram_odt1 = 0x00000030, 275a81b0fd6SJagan Teki .dram_sdba2 = 0x00000000, 276a81b0fd6SJagan Teki .dram_sdclk_0 = 0x00000008, 277a81b0fd6SJagan Teki .dram_sdqs0 = 0x00000038, 278a81b0fd6SJagan Teki .dram_sdqs1 = 0x00000030, 279a81b0fd6SJagan Teki .dram_reset = 0x00000030, 280a81b0fd6SJagan Teki }; 281a81b0fd6SJagan Teki 282a81b0fd6SJagan Teki static struct mx6_mmdc_calibration mx6_mmcd_calib = { 283a81b0fd6SJagan Teki .p0_mpwldectrl0 = 0x00070007, 284a81b0fd6SJagan Teki .p0_mpdgctrl0 = 0x41490145, 285a81b0fd6SJagan Teki .p0_mprddlctl = 0x40404546, 286a81b0fd6SJagan Teki .p0_mpwrdlctl = 0x4040524D, 287a81b0fd6SJagan Teki }; 288a81b0fd6SJagan Teki 289a81b0fd6SJagan Teki struct mx6_ddr_sysinfo ddr_sysinfo = { 290a81b0fd6SJagan Teki .dsize = 0, 291a81b0fd6SJagan Teki .cs_density = 20, 292a81b0fd6SJagan Teki .ncs = 1, 293a81b0fd6SJagan Teki .cs1_mirror = 0, 294a81b0fd6SJagan Teki .rtt_wr = 2, 295a81b0fd6SJagan Teki .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 296a81b0fd6SJagan Teki .walat = 1, /* Write additional latency */ 297a81b0fd6SJagan Teki .ralat = 5, /* Read additional latency */ 298a81b0fd6SJagan Teki .mif3_mode = 3, /* Command prediction working mode */ 299a81b0fd6SJagan Teki .bi_on = 1, /* Bank interleaving enabled */ 300a81b0fd6SJagan Teki .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 301a81b0fd6SJagan Teki .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 302a81b0fd6SJagan Teki .ddr_type = DDR_TYPE_DDR3, 303a81b0fd6SJagan Teki }; 304a81b0fd6SJagan Teki 305a81b0fd6SJagan Teki static struct mx6_ddr3_cfg mem_ddr = { 306a81b0fd6SJagan Teki .mem_speed = 800, 307a81b0fd6SJagan Teki .density = 4, 308a81b0fd6SJagan Teki .width = 16, 309a81b0fd6SJagan Teki .banks = 8, 310a81b0fd6SJagan Teki #ifdef TARGET_MX6UL_ISIOT 311a81b0fd6SJagan Teki .rowaddr = 15, 312a81b0fd6SJagan Teki #else 313a81b0fd6SJagan Teki .rowaddr = 13, 314a81b0fd6SJagan Teki #endif 315a81b0fd6SJagan Teki .coladdr = 10, 316a81b0fd6SJagan Teki .pagesz = 2, 317a81b0fd6SJagan Teki .trcd = 1375, 318a81b0fd6SJagan Teki .trcmin = 4875, 319a81b0fd6SJagan Teki .trasmin = 3500, 320a81b0fd6SJagan Teki }; 321a81b0fd6SJagan Teki #endif /* CONFIG_MX6UL */ 322d8de3c73SJagan Teki 323d8de3c73SJagan Teki static void ccgr_init(void) 324d8de3c73SJagan Teki { 325d8de3c73SJagan Teki struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 326d8de3c73SJagan Teki 327a81b0fd6SJagan Teki #ifdef CONFIG_MX6QDL 328d8de3c73SJagan Teki writel(0x00003F3F, &ccm->CCGR0); 329d8de3c73SJagan Teki writel(0x0030FC00, &ccm->CCGR1); 330d8de3c73SJagan Teki writel(0x000FC000, &ccm->CCGR2); 331d8de3c73SJagan Teki writel(0x3F300000, &ccm->CCGR3); 332d8de3c73SJagan Teki writel(0xFF00F300, &ccm->CCGR4); 333d8de3c73SJagan Teki writel(0x0F0000C3, &ccm->CCGR5); 334d8de3c73SJagan Teki writel(0x000003CC, &ccm->CCGR6); 335a81b0fd6SJagan Teki #elif CONFIG_MX6UL 336a81b0fd6SJagan Teki writel(0x00c03f3f, &ccm->CCGR0); 337a81b0fd6SJagan Teki writel(0xfcffff00, &ccm->CCGR1); 338a81b0fd6SJagan Teki writel(0x0cffffcc, &ccm->CCGR2); 339a81b0fd6SJagan Teki writel(0x3f3c3030, &ccm->CCGR3); 340a81b0fd6SJagan Teki writel(0xff00fffc, &ccm->CCGR4); 341a81b0fd6SJagan Teki writel(0x033f30ff, &ccm->CCGR5); 342a81b0fd6SJagan Teki writel(0x00c00fff, &ccm->CCGR6); 343a81b0fd6SJagan Teki #endif 344d8de3c73SJagan Teki } 345d8de3c73SJagan Teki 346d8de3c73SJagan Teki static void spl_dram_init(void) 347d8de3c73SJagan Teki { 348a81b0fd6SJagan Teki #ifdef CONFIG_MX6QDL 349d8de3c73SJagan Teki if (is_mx6solo()) { 350d8de3c73SJagan Teki mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 351d8de3c73SJagan Teki mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); 352d8de3c73SJagan Teki } else if (is_mx6dl()) { 353d8de3c73SJagan Teki mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 354d8de3c73SJagan Teki mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); 355d8de3c73SJagan Teki } else if (is_mx6dq()) { 356d8de3c73SJagan Teki mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); 357d8de3c73SJagan Teki mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); 358d8de3c73SJagan Teki } 359a81b0fd6SJagan Teki #elif CONFIG_MX6UL 360a81b0fd6SJagan Teki mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 361a81b0fd6SJagan Teki mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); 362a81b0fd6SJagan Teki #endif 363d8de3c73SJagan Teki 364d8de3c73SJagan Teki udelay(100); 365d8de3c73SJagan Teki } 366d8de3c73SJagan Teki 367d8de3c73SJagan Teki void board_init_f(ulong dummy) 368d8de3c73SJagan Teki { 369d8de3c73SJagan Teki ccgr_init(); 370d8de3c73SJagan Teki 371d8de3c73SJagan Teki /* setup AIPS and disable watchdog */ 372d8de3c73SJagan Teki arch_cpu_init(); 373d8de3c73SJagan Teki 374d8de3c73SJagan Teki gpr_init(); 375d8de3c73SJagan Teki 376d8de3c73SJagan Teki /* iomux */ 377a81b0fd6SJagan Teki SETUP_IOMUX_PADS(uart_pads); 378d8de3c73SJagan Teki 379d8de3c73SJagan Teki /* setup GP timer */ 380d8de3c73SJagan Teki timer_init(); 381d8de3c73SJagan Teki 382d8de3c73SJagan Teki /* UART clocks enabled and gd valid - init serial console */ 383d8de3c73SJagan Teki preloader_console_init(); 384d8de3c73SJagan Teki 385d8de3c73SJagan Teki /* DDR initialization */ 386d8de3c73SJagan Teki spl_dram_init(); 387d8de3c73SJagan Teki 388d8de3c73SJagan Teki /* Clear the BSS. */ 389d8de3c73SJagan Teki memset(__bss_start, 0, __bss_end - __bss_start); 390d8de3c73SJagan Teki 391d8de3c73SJagan Teki /* load/boot image from boot device */ 392d8de3c73SJagan Teki board_init_r(NULL, 0); 393d8de3c73SJagan Teki } 394