183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2d8de3c73SJagan Teki /* 3d8de3c73SJagan Teki * Copyright (C) 2016 Amarula Solutions B.V. 4d8de3c73SJagan Teki * Copyright (C) 2016 Engicam S.r.l. 5d8de3c73SJagan Teki * Author: Jagan Teki <jagan@amarulasolutions.com> 6d8de3c73SJagan Teki */ 7d8de3c73SJagan Teki 8d8de3c73SJagan Teki #include <common.h> 9d8de3c73SJagan Teki #include <spl.h> 10d8de3c73SJagan Teki 11d8de3c73SJagan Teki #include <asm/io.h> 12d8de3c73SJagan Teki #include <asm/gpio.h> 13d8de3c73SJagan Teki #include <linux/sizes.h> 14d8de3c73SJagan Teki 15d8de3c73SJagan Teki #include <asm/arch/clock.h> 16d8de3c73SJagan Teki #include <asm/arch/crm_regs.h> 17d8de3c73SJagan Teki #include <asm/arch/iomux.h> 18d8de3c73SJagan Teki #include <asm/arch/mx6-ddr.h> 19d8de3c73SJagan Teki #include <asm/arch/mx6-pins.h> 20d8de3c73SJagan Teki #include <asm/arch/sys_proto.h> 21d8de3c73SJagan Teki 22552a848eSStefano Babic #include <asm/mach-imx/iomux-v3.h> 23552a848eSStefano Babic #include <asm/mach-imx/video.h> 24d8de3c73SJagan Teki 25d8de3c73SJagan Teki #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 26d8de3c73SJagan Teki PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 27d8de3c73SJagan Teki PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 28d8de3c73SJagan Teki 29a81b0fd6SJagan Teki static iomux_v3_cfg_t const uart_pads[] = { 30a81b0fd6SJagan Teki #ifdef CONFIG_MX6QDL 31d8de3c73SJagan Teki IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 32d8de3c73SJagan Teki IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 33a81b0fd6SJagan Teki #elif CONFIG_MX6UL 34a81b0fd6SJagan Teki IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)), 35a81b0fd6SJagan Teki IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)), 36a81b0fd6SJagan Teki #endif 37d8de3c73SJagan Teki }; 38d8de3c73SJagan Teki 39a1797beeSJagan Teki #ifdef CONFIG_SPL_LOAD_FIT 40a1797beeSJagan Teki int board_fit_config_name_match(const char *name) 41a1797beeSJagan Teki { 42a1797beeSJagan Teki if (is_mx6dq() && !strcmp(name, "imx6q-icore")) 43a1797beeSJagan Teki return 0; 44a1797beeSJagan Teki else if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs")) 45a1797beeSJagan Teki return 0; 4682e8ba05SJagan Teki else if (is_mx6dq() && !strcmp(name, "imx6q-icore-mipi")) 4782e8ba05SJagan Teki return 0; 48a1797beeSJagan Teki else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore")) 49a1797beeSJagan Teki return 0; 50a1797beeSJagan Teki else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs")) 51a1797beeSJagan Teki return 0; 5282e8ba05SJagan Teki else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-mipi")) 5382e8ba05SJagan Teki return 0; 54a1797beeSJagan Teki else 55a1797beeSJagan Teki return -1; 56a1797beeSJagan Teki } 57a1797beeSJagan Teki #endif 58a1797beeSJagan Teki 5952aaddd6SJagan Teki #ifdef CONFIG_ENV_IS_IN_MMC 6052aaddd6SJagan Teki void board_boot_order(u32 *spl_boot_list) 6152aaddd6SJagan Teki { 6252aaddd6SJagan Teki u32 bmode = imx6_src_get_boot_mode(); 6352aaddd6SJagan Teki u8 boot_dev = BOOT_DEVICE_MMC1; 6452aaddd6SJagan Teki 6552aaddd6SJagan Teki switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) { 6652aaddd6SJagan Teki case IMX6_BMODE_SD: 6752aaddd6SJagan Teki case IMX6_BMODE_ESD: 6852aaddd6SJagan Teki /* SD/eSD - BOOT_DEVICE_MMC1 */ 6952aaddd6SJagan Teki break; 7052aaddd6SJagan Teki case IMX6_BMODE_MMC: 7152aaddd6SJagan Teki case IMX6_BMODE_EMMC: 7252aaddd6SJagan Teki /* MMC/eMMC */ 7352aaddd6SJagan Teki boot_dev = BOOT_DEVICE_MMC2; 7452aaddd6SJagan Teki break; 7552aaddd6SJagan Teki default: 7652aaddd6SJagan Teki /* Default - BOOT_DEVICE_MMC1 */ 7752aaddd6SJagan Teki printf("Wrong board boot order\n"); 7852aaddd6SJagan Teki break; 7952aaddd6SJagan Teki } 8052aaddd6SJagan Teki 8152aaddd6SJagan Teki spl_boot_list[0] = boot_dev; 8252aaddd6SJagan Teki } 8352aaddd6SJagan Teki #endif 8452aaddd6SJagan Teki 8563af4b0aSJagan Teki #ifdef CONFIG_SPL_OS_BOOT 8663af4b0aSJagan Teki int spl_start_uboot(void) 8763af4b0aSJagan Teki { 8863af4b0aSJagan Teki /* break into full u-boot on 'c' */ 8963af4b0aSJagan Teki if (serial_tstc() && serial_getc() == 'c') 9063af4b0aSJagan Teki return 1; 9163af4b0aSJagan Teki 9263af4b0aSJagan Teki return 0; 9363af4b0aSJagan Teki } 9463af4b0aSJagan Teki #endif 9563af4b0aSJagan Teki 96a81b0fd6SJagan Teki #ifdef CONFIG_MX6QDL 97d8de3c73SJagan Teki /* 98d8de3c73SJagan Teki * Driving strength: 99d8de3c73SJagan Teki * 0x30 == 40 Ohm 100d8de3c73SJagan Teki * 0x28 == 48 Ohm 101d8de3c73SJagan Teki */ 102d8de3c73SJagan Teki #define IMX6DQ_DRIVE_STRENGTH 0x30 103d8de3c73SJagan Teki #define IMX6SDL_DRIVE_STRENGTH 0x28 104d8de3c73SJagan Teki 105d8de3c73SJagan Teki /* configure MX6Q/DUAL mmdc DDR io registers */ 106d8de3c73SJagan Teki static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { 107d8de3c73SJagan Teki .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, 108d8de3c73SJagan Teki .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, 109d8de3c73SJagan Teki .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, 110d8de3c73SJagan Teki .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, 111d8de3c73SJagan Teki .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, 112d8de3c73SJagan Teki .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, 113d8de3c73SJagan Teki .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, 114d8de3c73SJagan Teki .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, 115d8de3c73SJagan Teki .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, 116d8de3c73SJagan Teki .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, 117d8de3c73SJagan Teki .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, 118d8de3c73SJagan Teki .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, 119d8de3c73SJagan Teki .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, 120d8de3c73SJagan Teki .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, 121d8de3c73SJagan Teki .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, 122d8de3c73SJagan Teki .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, 123d8de3c73SJagan Teki .dram_cas = IMX6DQ_DRIVE_STRENGTH, 124d8de3c73SJagan Teki .dram_ras = IMX6DQ_DRIVE_STRENGTH, 125d8de3c73SJagan Teki .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, 126d8de3c73SJagan Teki .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, 127d8de3c73SJagan Teki .dram_reset = IMX6DQ_DRIVE_STRENGTH, 128d8de3c73SJagan Teki .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH, 129d8de3c73SJagan Teki .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH, 130d8de3c73SJagan Teki .dram_sdba2 = 0x00000000, 131d8de3c73SJagan Teki .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, 132d8de3c73SJagan Teki .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, 133d8de3c73SJagan Teki }; 134d8de3c73SJagan Teki 135d8de3c73SJagan Teki /* configure MX6Q/DUAL mmdc GRP io registers */ 136d8de3c73SJagan Teki static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { 137d8de3c73SJagan Teki .grp_b0ds = IMX6DQ_DRIVE_STRENGTH, 138d8de3c73SJagan Teki .grp_b1ds = IMX6DQ_DRIVE_STRENGTH, 139d8de3c73SJagan Teki .grp_b2ds = IMX6DQ_DRIVE_STRENGTH, 140d8de3c73SJagan Teki .grp_b3ds = IMX6DQ_DRIVE_STRENGTH, 141d8de3c73SJagan Teki .grp_b4ds = IMX6DQ_DRIVE_STRENGTH, 142d8de3c73SJagan Teki .grp_b5ds = IMX6DQ_DRIVE_STRENGTH, 143d8de3c73SJagan Teki .grp_b6ds = IMX6DQ_DRIVE_STRENGTH, 144d8de3c73SJagan Teki .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, 145d8de3c73SJagan Teki .grp_addds = IMX6DQ_DRIVE_STRENGTH, 146d8de3c73SJagan Teki .grp_ddrmode_ctl = 0x00020000, 147d8de3c73SJagan Teki .grp_ddrpke = 0x00000000, 148d8de3c73SJagan Teki .grp_ddrmode = 0x00020000, 149d8de3c73SJagan Teki .grp_ctlds = IMX6DQ_DRIVE_STRENGTH, 150d8de3c73SJagan Teki .grp_ddr_type = 0x000c0000, 151d8de3c73SJagan Teki }; 152d8de3c73SJagan Teki 153d8de3c73SJagan Teki /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ 154d8de3c73SJagan Teki struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { 155d8de3c73SJagan Teki .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, 156d8de3c73SJagan Teki .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, 157d8de3c73SJagan Teki .dram_cas = IMX6SDL_DRIVE_STRENGTH, 158d8de3c73SJagan Teki .dram_ras = IMX6SDL_DRIVE_STRENGTH, 159d8de3c73SJagan Teki .dram_reset = IMX6SDL_DRIVE_STRENGTH, 160d8de3c73SJagan Teki .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, 161d8de3c73SJagan Teki .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, 162d8de3c73SJagan Teki .dram_sdba2 = 0x00000000, 163d8de3c73SJagan Teki .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, 164d8de3c73SJagan Teki .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, 165d8de3c73SJagan Teki .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, 166d8de3c73SJagan Teki .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, 167d8de3c73SJagan Teki .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, 168d8de3c73SJagan Teki .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, 169d8de3c73SJagan Teki .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, 170d8de3c73SJagan Teki .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, 171d8de3c73SJagan Teki .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, 172d8de3c73SJagan Teki .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, 173d8de3c73SJagan Teki .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, 174d8de3c73SJagan Teki .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, 175d8de3c73SJagan Teki .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, 176d8de3c73SJagan Teki .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, 177d8de3c73SJagan Teki .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, 178d8de3c73SJagan Teki .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, 179d8de3c73SJagan Teki .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, 180d8de3c73SJagan Teki .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, 181d8de3c73SJagan Teki }; 182d8de3c73SJagan Teki 183d8de3c73SJagan Teki /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ 184d8de3c73SJagan Teki struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { 185d8de3c73SJagan Teki .grp_ddr_type = 0x000c0000, 186d8de3c73SJagan Teki .grp_ddrmode_ctl = 0x00020000, 187d8de3c73SJagan Teki .grp_ddrpke = 0x00000000, 188d8de3c73SJagan Teki .grp_addds = IMX6SDL_DRIVE_STRENGTH, 189d8de3c73SJagan Teki .grp_ctlds = IMX6SDL_DRIVE_STRENGTH, 190d8de3c73SJagan Teki .grp_ddrmode = 0x00020000, 191d8de3c73SJagan Teki .grp_b0ds = IMX6SDL_DRIVE_STRENGTH, 192d8de3c73SJagan Teki .grp_b1ds = IMX6SDL_DRIVE_STRENGTH, 193d8de3c73SJagan Teki .grp_b2ds = IMX6SDL_DRIVE_STRENGTH, 194d8de3c73SJagan Teki .grp_b3ds = IMX6SDL_DRIVE_STRENGTH, 195d8de3c73SJagan Teki .grp_b4ds = IMX6SDL_DRIVE_STRENGTH, 196d8de3c73SJagan Teki .grp_b5ds = IMX6SDL_DRIVE_STRENGTH, 197d8de3c73SJagan Teki .grp_b6ds = IMX6SDL_DRIVE_STRENGTH, 198d8de3c73SJagan Teki .grp_b7ds = IMX6SDL_DRIVE_STRENGTH, 199d8de3c73SJagan Teki }; 200d8de3c73SJagan Teki 201d8de3c73SJagan Teki /* mt41j256 */ 202d8de3c73SJagan Teki static struct mx6_ddr3_cfg mt41j256 = { 203d8de3c73SJagan Teki .mem_speed = 1066, 204d8de3c73SJagan Teki .density = 2, 205d8de3c73SJagan Teki .width = 16, 206d8de3c73SJagan Teki .banks = 8, 207d8de3c73SJagan Teki .rowaddr = 13, 208d8de3c73SJagan Teki .coladdr = 10, 209d8de3c73SJagan Teki .pagesz = 2, 210d8de3c73SJagan Teki .trcd = 1375, 211d8de3c73SJagan Teki .trcmin = 4875, 212d8de3c73SJagan Teki .trasmin = 3500, 213d8de3c73SJagan Teki .SRT = 0, 214d8de3c73SJagan Teki }; 215d8de3c73SJagan Teki 216d8de3c73SJagan Teki static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { 217d8de3c73SJagan Teki .p0_mpwldectrl0 = 0x000E0009, 218d8de3c73SJagan Teki .p0_mpwldectrl1 = 0x0018000E, 219d8de3c73SJagan Teki .p1_mpwldectrl0 = 0x00000007, 220d8de3c73SJagan Teki .p1_mpwldectrl1 = 0x00000000, 221d8de3c73SJagan Teki .p0_mpdgctrl0 = 0x43280334, 222d8de3c73SJagan Teki .p0_mpdgctrl1 = 0x031C0314, 223d8de3c73SJagan Teki .p1_mpdgctrl0 = 0x4318031C, 224d8de3c73SJagan Teki .p1_mpdgctrl1 = 0x030C0258, 225d8de3c73SJagan Teki .p0_mprddlctl = 0x3E343A40, 226d8de3c73SJagan Teki .p1_mprddlctl = 0x383C3844, 227d8de3c73SJagan Teki .p0_mpwrdlctl = 0x40404440, 228d8de3c73SJagan Teki .p1_mpwrdlctl = 0x4C3E4446, 229d8de3c73SJagan Teki }; 230d8de3c73SJagan Teki 231d8de3c73SJagan Teki /* DDR 64bit */ 232d8de3c73SJagan Teki static struct mx6_ddr_sysinfo mem_q = { 233d8de3c73SJagan Teki .ddr_type = DDR_TYPE_DDR3, 234d8de3c73SJagan Teki .dsize = 2, 235d8de3c73SJagan Teki .cs1_mirror = 0, 236d8de3c73SJagan Teki /* config for full 4GB range so that get_mem_size() works */ 237d8de3c73SJagan Teki .cs_density = 32, 238d8de3c73SJagan Teki .ncs = 1, 239d8de3c73SJagan Teki .bi_on = 1, 240d8de3c73SJagan Teki .rtt_nom = 2, 241d8de3c73SJagan Teki .rtt_wr = 2, 242d8de3c73SJagan Teki .ralat = 5, 243d8de3c73SJagan Teki .walat = 0, 244d8de3c73SJagan Teki .mif3_mode = 3, 245d8de3c73SJagan Teki .rst_to_cke = 0x23, 246d8de3c73SJagan Teki .sde_to_rst = 0x10, 247d8de3c73SJagan Teki }; 248d8de3c73SJagan Teki 249d8de3c73SJagan Teki static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { 250d8de3c73SJagan Teki .p0_mpwldectrl0 = 0x001F0024, 251d8de3c73SJagan Teki .p0_mpwldectrl1 = 0x00110018, 252d8de3c73SJagan Teki .p1_mpwldectrl0 = 0x001F0024, 253d8de3c73SJagan Teki .p1_mpwldectrl1 = 0x00110018, 254d8de3c73SJagan Teki .p0_mpdgctrl0 = 0x4230022C, 255d8de3c73SJagan Teki .p0_mpdgctrl1 = 0x02180220, 256d8de3c73SJagan Teki .p1_mpdgctrl0 = 0x42440248, 257d8de3c73SJagan Teki .p1_mpdgctrl1 = 0x02300238, 258d8de3c73SJagan Teki .p0_mprddlctl = 0x44444A48, 259d8de3c73SJagan Teki .p1_mprddlctl = 0x46484A42, 260d8de3c73SJagan Teki .p0_mpwrdlctl = 0x38383234, 261d8de3c73SJagan Teki .p1_mpwrdlctl = 0x3C34362E, 262d8de3c73SJagan Teki }; 263d8de3c73SJagan Teki 264d8de3c73SJagan Teki /* DDR 64bit 1GB */ 265d8de3c73SJagan Teki static struct mx6_ddr_sysinfo mem_dl = { 266d8de3c73SJagan Teki .dsize = 2, 267d8de3c73SJagan Teki .cs1_mirror = 0, 268d8de3c73SJagan Teki /* config for full 4GB range so that get_mem_size() works */ 269d8de3c73SJagan Teki .cs_density = 32, 270d8de3c73SJagan Teki .ncs = 1, 271d8de3c73SJagan Teki .bi_on = 1, 272d8de3c73SJagan Teki .rtt_nom = 1, 273d8de3c73SJagan Teki .rtt_wr = 1, 274d8de3c73SJagan Teki .ralat = 5, 275d8de3c73SJagan Teki .walat = 0, 276d8de3c73SJagan Teki .mif3_mode = 3, 277d8de3c73SJagan Teki .rst_to_cke = 0x23, 278d8de3c73SJagan Teki .sde_to_rst = 0x10, 279d8de3c73SJagan Teki }; 280d8de3c73SJagan Teki 281d8de3c73SJagan Teki /* DDR 32bit 512MB */ 282d8de3c73SJagan Teki static struct mx6_ddr_sysinfo mem_s = { 283d8de3c73SJagan Teki .dsize = 1, 284d8de3c73SJagan Teki .cs1_mirror = 0, 285d8de3c73SJagan Teki /* config for full 4GB range so that get_mem_size() works */ 286d8de3c73SJagan Teki .cs_density = 32, 287d8de3c73SJagan Teki .ncs = 1, 288d8de3c73SJagan Teki .bi_on = 1, 289d8de3c73SJagan Teki .rtt_nom = 1, 290d8de3c73SJagan Teki .rtt_wr = 1, 291d8de3c73SJagan Teki .ralat = 5, 292d8de3c73SJagan Teki .walat = 0, 293d8de3c73SJagan Teki .mif3_mode = 3, 294d8de3c73SJagan Teki .rst_to_cke = 0x23, 295d8de3c73SJagan Teki .sde_to_rst = 0x10, 296d8de3c73SJagan Teki }; 297a81b0fd6SJagan Teki #endif /* CONFIG_MX6QDL */ 298a81b0fd6SJagan Teki 299a81b0fd6SJagan Teki #ifdef CONFIG_MX6UL 300a81b0fd6SJagan Teki static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { 301a81b0fd6SJagan Teki .grp_addds = 0x00000030, 302a81b0fd6SJagan Teki .grp_ddrmode_ctl = 0x00020000, 303a81b0fd6SJagan Teki .grp_b0ds = 0x00000030, 304a81b0fd6SJagan Teki .grp_ctlds = 0x00000030, 305a81b0fd6SJagan Teki .grp_b1ds = 0x00000030, 306a81b0fd6SJagan Teki .grp_ddrpke = 0x00000000, 307a81b0fd6SJagan Teki .grp_ddrmode = 0x00020000, 308a81b0fd6SJagan Teki .grp_ddr_type = 0x000c0000, 309a81b0fd6SJagan Teki }; 310a81b0fd6SJagan Teki 311a81b0fd6SJagan Teki static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 312a81b0fd6SJagan Teki .dram_dqm0 = 0x00000030, 313a81b0fd6SJagan Teki .dram_dqm1 = 0x00000030, 314a81b0fd6SJagan Teki .dram_ras = 0x00000030, 315a81b0fd6SJagan Teki .dram_cas = 0x00000030, 316a81b0fd6SJagan Teki .dram_odt0 = 0x00000030, 317a81b0fd6SJagan Teki .dram_odt1 = 0x00000030, 318a81b0fd6SJagan Teki .dram_sdba2 = 0x00000000, 319a81b0fd6SJagan Teki .dram_sdclk_0 = 0x00000008, 320a81b0fd6SJagan Teki .dram_sdqs0 = 0x00000038, 321a81b0fd6SJagan Teki .dram_sdqs1 = 0x00000030, 322a81b0fd6SJagan Teki .dram_reset = 0x00000030, 323a81b0fd6SJagan Teki }; 324a81b0fd6SJagan Teki 325a81b0fd6SJagan Teki static struct mx6_mmdc_calibration mx6_mmcd_calib = { 326a81b0fd6SJagan Teki .p0_mpwldectrl0 = 0x00070007, 327a81b0fd6SJagan Teki .p0_mpdgctrl0 = 0x41490145, 328a81b0fd6SJagan Teki .p0_mprddlctl = 0x40404546, 329a81b0fd6SJagan Teki .p0_mpwrdlctl = 0x4040524D, 330a81b0fd6SJagan Teki }; 331a81b0fd6SJagan Teki 332a81b0fd6SJagan Teki struct mx6_ddr_sysinfo ddr_sysinfo = { 333a81b0fd6SJagan Teki .dsize = 0, 334a81b0fd6SJagan Teki .cs_density = 20, 335a81b0fd6SJagan Teki .ncs = 1, 336a81b0fd6SJagan Teki .cs1_mirror = 0, 337a81b0fd6SJagan Teki .rtt_wr = 2, 338a81b0fd6SJagan Teki .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 339a81b0fd6SJagan Teki .walat = 1, /* Write additional latency */ 340a81b0fd6SJagan Teki .ralat = 5, /* Read additional latency */ 341a81b0fd6SJagan Teki .mif3_mode = 3, /* Command prediction working mode */ 342a81b0fd6SJagan Teki .bi_on = 1, /* Bank interleaving enabled */ 343a81b0fd6SJagan Teki .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 344a81b0fd6SJagan Teki .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 345a81b0fd6SJagan Teki .ddr_type = DDR_TYPE_DDR3, 346a81b0fd6SJagan Teki }; 347a81b0fd6SJagan Teki 348a81b0fd6SJagan Teki static struct mx6_ddr3_cfg mem_ddr = { 349a81b0fd6SJagan Teki .mem_speed = 800, 350a81b0fd6SJagan Teki .density = 4, 351a81b0fd6SJagan Teki .width = 16, 352a81b0fd6SJagan Teki .banks = 8, 353a81b0fd6SJagan Teki #ifdef TARGET_MX6UL_ISIOT 354a81b0fd6SJagan Teki .rowaddr = 15, 355a81b0fd6SJagan Teki #else 356a81b0fd6SJagan Teki .rowaddr = 13, 357a81b0fd6SJagan Teki #endif 358a81b0fd6SJagan Teki .coladdr = 10, 359a81b0fd6SJagan Teki .pagesz = 2, 360a81b0fd6SJagan Teki .trcd = 1375, 361a81b0fd6SJagan Teki .trcmin = 4875, 362a81b0fd6SJagan Teki .trasmin = 3500, 363a81b0fd6SJagan Teki }; 364a81b0fd6SJagan Teki #endif /* CONFIG_MX6UL */ 365d8de3c73SJagan Teki 366d8de3c73SJagan Teki static void ccgr_init(void) 367d8de3c73SJagan Teki { 368d8de3c73SJagan Teki struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 369d8de3c73SJagan Teki 370a81b0fd6SJagan Teki #ifdef CONFIG_MX6QDL 371d8de3c73SJagan Teki writel(0x00003F3F, &ccm->CCGR0); 372d8de3c73SJagan Teki writel(0x0030FC00, &ccm->CCGR1); 373d8de3c73SJagan Teki writel(0x000FC000, &ccm->CCGR2); 374d8de3c73SJagan Teki writel(0x3F300000, &ccm->CCGR3); 375d8de3c73SJagan Teki writel(0xFF00F300, &ccm->CCGR4); 376d8de3c73SJagan Teki writel(0x0F0000C3, &ccm->CCGR5); 377d8de3c73SJagan Teki writel(0x000003CC, &ccm->CCGR6); 378a81b0fd6SJagan Teki #elif CONFIG_MX6UL 379a81b0fd6SJagan Teki writel(0x00c03f3f, &ccm->CCGR0); 380a81b0fd6SJagan Teki writel(0xfcffff00, &ccm->CCGR1); 381a81b0fd6SJagan Teki writel(0x0cffffcc, &ccm->CCGR2); 382a81b0fd6SJagan Teki writel(0x3f3c3030, &ccm->CCGR3); 383a81b0fd6SJagan Teki writel(0xff00fffc, &ccm->CCGR4); 384a81b0fd6SJagan Teki writel(0x033f30ff, &ccm->CCGR5); 385a81b0fd6SJagan Teki writel(0x00c00fff, &ccm->CCGR6); 386a81b0fd6SJagan Teki #endif 387d8de3c73SJagan Teki } 388d8de3c73SJagan Teki 389d8de3c73SJagan Teki static void spl_dram_init(void) 390d8de3c73SJagan Teki { 391a81b0fd6SJagan Teki #ifdef CONFIG_MX6QDL 392d8de3c73SJagan Teki if (is_mx6solo()) { 393d8de3c73SJagan Teki mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 394d8de3c73SJagan Teki mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); 395d8de3c73SJagan Teki } else if (is_mx6dl()) { 396d8de3c73SJagan Teki mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 397d8de3c73SJagan Teki mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); 398d8de3c73SJagan Teki } else if (is_mx6dq()) { 399d8de3c73SJagan Teki mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); 400d8de3c73SJagan Teki mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); 401d8de3c73SJagan Teki } 402a81b0fd6SJagan Teki #elif CONFIG_MX6UL 403a81b0fd6SJagan Teki mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 404a81b0fd6SJagan Teki mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); 405a81b0fd6SJagan Teki #endif 406d8de3c73SJagan Teki 407d8de3c73SJagan Teki udelay(100); 408d8de3c73SJagan Teki } 409d8de3c73SJagan Teki 410d8de3c73SJagan Teki void board_init_f(ulong dummy) 411d8de3c73SJagan Teki { 412d8de3c73SJagan Teki ccgr_init(); 413d8de3c73SJagan Teki 414d8de3c73SJagan Teki /* setup AIPS and disable watchdog */ 415d8de3c73SJagan Teki arch_cpu_init(); 416d8de3c73SJagan Teki 417*30588799SMichael Trimarchi if (!(is_mx6ul())) 418d8de3c73SJagan Teki gpr_init(); 419d8de3c73SJagan Teki 420d8de3c73SJagan Teki /* iomux */ 421a81b0fd6SJagan Teki SETUP_IOMUX_PADS(uart_pads); 422d8de3c73SJagan Teki 423d8de3c73SJagan Teki /* setup GP timer */ 424d8de3c73SJagan Teki timer_init(); 425d8de3c73SJagan Teki 426d8de3c73SJagan Teki /* UART clocks enabled and gd valid - init serial console */ 427d8de3c73SJagan Teki preloader_console_init(); 428d8de3c73SJagan Teki 429d8de3c73SJagan Teki /* DDR initialization */ 430d8de3c73SJagan Teki spl_dram_init(); 431d8de3c73SJagan Teki } 432