1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * mux.c 4 * 5 * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ 6 * 7 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 8 */ 9 10 #include <common.h> 11 #include <asm/arch/sys_proto.h> 12 #include <asm/arch/hardware.h> 13 #include <asm/arch/mux.h> 14 #include <asm/io.h> 15 #include <i2c.h> 16 #include "board.h" 17 18 static struct module_pin_mux uart0_pin_mux[] = { 19 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ 20 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ 21 {-1}, 22 }; 23 24 static struct module_pin_mux uart1_pin_mux[] = { 25 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ 26 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ 27 {-1}, 28 }; 29 30 static struct module_pin_mux uart2_pin_mux[] = { 31 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ 32 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ 33 {-1}, 34 }; 35 36 static struct module_pin_mux uart3_pin_mux[] = { 37 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ 38 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ 39 {-1}, 40 }; 41 42 static struct module_pin_mux uart4_pin_mux[] = { 43 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ 44 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ 45 {-1}, 46 }; 47 48 static struct module_pin_mux uart5_pin_mux[] = { 49 {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ 50 {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ 51 {-1}, 52 }; 53 54 static struct module_pin_mux i2c0_pin_mux[] = { 55 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | 56 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ 57 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | 58 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ 59 {-1}, 60 }; 61 62 void enable_uart0_pin_mux(void) 63 { 64 configure_module_pin_mux(uart0_pin_mux); 65 } 66 67 void enable_uart1_pin_mux(void) 68 { 69 configure_module_pin_mux(uart1_pin_mux); 70 } 71 72 void enable_uart2_pin_mux(void) 73 { 74 configure_module_pin_mux(uart2_pin_mux); 75 } 76 77 void enable_uart3_pin_mux(void) 78 { 79 configure_module_pin_mux(uart3_pin_mux); 80 } 81 82 void enable_uart4_pin_mux(void) 83 { 84 configure_module_pin_mux(uart4_pin_mux); 85 } 86 87 void enable_uart5_pin_mux(void) 88 { 89 configure_module_pin_mux(uart5_pin_mux); 90 } 91 92 void enable_uart_pin_mux(u32 addr) 93 { 94 switch (addr) { 95 case CONFIG_SYS_NS16550_COM1: 96 enable_uart0_pin_mux(); 97 break; 98 case CONFIG_SYS_NS16550_COM2: 99 enable_uart1_pin_mux(); 100 break; 101 case CONFIG_SYS_NS16550_COM3: 102 enable_uart2_pin_mux(); 103 break; 104 case CONFIG_SYS_NS16550_COM4: 105 enable_uart3_pin_mux(); 106 break; 107 case CONFIG_SYS_NS16550_COM5: 108 enable_uart4_pin_mux(); 109 break; 110 case CONFIG_SYS_NS16550_COM6: 111 enable_uart5_pin_mux(); 112 break; 113 } 114 } 115 116 void enable_i2c0_pin_mux(void) 117 { 118 configure_module_pin_mux(i2c0_pin_mux); 119 } 120