xref: /openbmc/u-boot/board/eets/pdu001/board.h (revision 85ab0452)
1*85ab0452SFelix Brack /*
2*85ab0452SFelix Brack  * board.h
3*85ab0452SFelix Brack  *
4*85ab0452SFelix Brack  * EETS GmbH PDU001 board information header
5*85ab0452SFelix Brack  *
6*85ab0452SFelix Brack  * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
7*85ab0452SFelix Brack  *
8*85ab0452SFelix Brack  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
9*85ab0452SFelix Brack  *
10*85ab0452SFelix Brack  * SPDX-License-Identifier: GPL-2.0+
11*85ab0452SFelix Brack  */
12*85ab0452SFelix Brack 
13*85ab0452SFelix Brack #ifndef _BOARD_H_
14*85ab0452SFelix Brack #define _BOARD_H_
15*85ab0452SFelix Brack 
16*85ab0452SFelix Brack /*
17*85ab0452SFelix Brack  * We have two pin mux functions that must exist. First we need I2C0 to
18*85ab0452SFelix Brack  * access the TPS65910 PMIC located on the M2 computing module.
19*85ab0452SFelix Brack  * Second, if we want low-level debugging or a early UART (ie. before the
20*85ab0452SFelix Brack  * pin controller driver is running), we need one of the UART ports UART0 to
21*85ab0452SFelix Brack  * UART5 (usually UART3 since it is wired to K2).
22*85ab0452SFelix Brack  * In case of I2C0 access we explicitly don't rely on the the ROM but we could
23*85ab0452SFelix Brack  * do so as we use the primary mode (mode 0) for I2C0.
24*85ab0452SFelix Brack  * All other multiplexing and pin configuration is done by the DT once it
25*85ab0452SFelix Brack  * gets parsed by the pin controller driver.
26*85ab0452SFelix Brack  * However we relay on the ROM to configure the pins of MMC0 (eMMC) as well
27*85ab0452SFelix Brack  * as MMC1 (microSD card-cage) since these are our boot devices.
28*85ab0452SFelix Brack  */
29*85ab0452SFelix Brack void enable_uart0_pin_mux(void);
30*85ab0452SFelix Brack void enable_uart1_pin_mux(void);
31*85ab0452SFelix Brack void enable_uart2_pin_mux(void);
32*85ab0452SFelix Brack void enable_uart3_pin_mux(void);
33*85ab0452SFelix Brack void enable_uart4_pin_mux(void);
34*85ab0452SFelix Brack void enable_uart5_pin_mux(void);
35*85ab0452SFelix Brack void enable_uart_pin_mux(u32 addr);
36*85ab0452SFelix Brack void enable_i2c0_pin_mux(void);
37*85ab0452SFelix Brack 
38*85ab0452SFelix Brack #endif
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