1 /* 2 * board.c 3 * 4 * Board functions for EETS PDU001 board 5 * 6 * Copyright (C) 2018, EETS GmbH, http://www.eets.ch/ 7 * 8 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <errno.h> 15 #include <spl.h> 16 #include <i2c.h> 17 #include <environment.h> 18 #include <watchdog.h> 19 #include <debug_uart.h> 20 #include <dm/ofnode.h> 21 #include <power/pmic.h> 22 #include <power/regulator.h> 23 #include <asm/arch/cpu.h> 24 #include <asm/arch/hardware.h> 25 #include <asm/arch/omap.h> 26 #include <asm/arch/ddr_defs.h> 27 #include <asm/arch/clock.h> 28 #include <asm/arch/gpio.h> 29 #include <asm/arch/mmc_host_def.h> 30 #include <asm/arch/sys_proto.h> 31 #include <asm/arch/mem.h> 32 #include <asm/io.h> 33 #include <asm/emif.h> 34 #include <asm/gpio.h> 35 #include "board.h" 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 #define I2C_ADDR_NODE_ID 0x50 40 #define I2C_REG_NODE_ID_BASE 0xfa 41 #define NODE_ID_BYTE_COUNT 6 42 43 #define I2C_ADDR_LEDS 0x60 44 #define I2C_REG_RUN_LED 0x06 45 #define RUN_LED_OFF 0x0 46 #define RUN_LED_RED 0x1 47 #define RUN_LED_GREEN (0x1 << 2) 48 49 #define VDD_MPU_REGULATOR "regulator@2" 50 #define VDD_CORE_REGULATOR "regulator@3" 51 #define DEFAULT_CORE_VOLTAGE 1137500 52 53 /* 54 * boot device save register 55 * ------------------------- 56 * The boot device can be quired by 'spl_boot_device()' in 57 * 'am33xx_spl_board_init'. However it can't be saved in the u-boot 58 * environment here. In turn 'spl_boot_device' can't be called in 59 * 'board_late_init' which allows writing to u-boot environment. 60 * To get the boot device from 'am33xx_spl_board_init' to 61 * 'board_late_init' we therefore use a scratch register from the RTC. 62 */ 63 #define CONFIG_SYS_RTC_SCRATCH0 0x60 64 #define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CONFIG_SYS_RTC_SCRATCH0) 65 66 #ifdef CONFIG_SPL_BUILD 67 static void save_boot_device(void) 68 { 69 *((u32 *)(BOOT_DEVICE_SAVE_REGISTER)) = spl_boot_device(); 70 } 71 #endif 72 73 u32 boot_device(void) 74 { 75 return *((u32 *)(BOOT_DEVICE_SAVE_REGISTER)); 76 } 77 78 /* Store the boot device in the environment variable 'boot_device' */ 79 static void env_set_boot_device(void) 80 { 81 switch (boot_device()) { 82 case BOOT_DEVICE_MMC1: { 83 env_set("boot_device", "emmc"); 84 break; 85 } 86 case BOOT_DEVICE_MMC2: { 87 env_set("boot_device", "sdcard"); 88 break; 89 } 90 default: { 91 env_set("boot_device", "unknown"); 92 break; 93 } 94 } 95 } 96 97 static void set_run_led(struct udevice *dev) 98 { 99 int val = RUN_LED_OFF; 100 101 if (IS_ENABLED(CONFIG_RUN_LED_RED)) 102 val = RUN_LED_RED; 103 else if (IS_ENABLED(CONFIG_RUN_LED_GREEN)) 104 val = RUN_LED_GREEN; 105 106 dm_i2c_reg_write(dev, I2C_REG_RUN_LED, val); 107 } 108 109 /* Set 'serial#' to the EUI-48 value of board node ID chip */ 110 static void env_set_serial(struct udevice *dev) 111 { 112 int val; 113 char serial[2 * NODE_ID_BYTE_COUNT + 1]; 114 int n; 115 116 for (n = 0; n < sizeof(serial); n += 2) { 117 val = dm_i2c_reg_read(dev, I2C_REG_NODE_ID_BASE + n / 2); 118 sprintf(serial + n, "%02X", val); 119 } 120 serial[2 * NODE_ID_BYTE_COUNT] = '\0'; 121 env_set("serial#", serial); 122 } 123 124 static void set_mpu_and_core_voltage(void) 125 { 126 int mpu_vdd; 127 int sil_rev; 128 struct udevice *dev; 129 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 130 131 /* 132 * The PDU001 (more precisely the computing module m2) uses a 133 * TPS65910 PMIC. For all MPU frequencies we support we use a CORE 134 * voltage of 1.1375V. For MPU voltage we need to switch based on 135 * the frequency we are running at. 136 */ 137 138 /* 139 * Depending on MPU clock and PG we will need a different VDD 140 * to drive at that speed. 141 */ 142 sil_rev = readl(&cdev->deviceid) >> 28; 143 mpu_vdd = am335x_get_mpu_vdd(sil_rev, dpll_mpu_opp100.m); 144 145 /* first update the MPU voltage */ 146 if (!regulator_get_by_devname(VDD_MPU_REGULATOR, &dev)) { 147 if (regulator_set_value(dev, mpu_vdd)) 148 debug("failed to set MPU voltage\n"); 149 } else { 150 debug("invalid MPU voltage ragulator %s\n", VDD_MPU_REGULATOR); 151 } 152 153 /* second update the CORE voltage */ 154 if (!regulator_get_by_devname(VDD_CORE_REGULATOR, &dev)) { 155 if (regulator_set_value(dev, DEFAULT_CORE_VOLTAGE)) 156 debug("failed to set CORE voltage\n"); 157 } else { 158 debug("invalid CORE voltage ragulator %s\n", 159 VDD_CORE_REGULATOR); 160 } 161 } 162 163 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 164 static const struct ddr_data ddr2_data = { 165 .datardsratio0 = MT47H128M16RT25E_RD_DQS, 166 .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, 167 .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, 168 }; 169 170 static const struct cmd_control ddr2_cmd_ctrl_data = { 171 .cmd0csratio = MT47H128M16RT25E_RATIO, 172 .cmd1csratio = MT47H128M16RT25E_RATIO, 173 .cmd2csratio = MT47H128M16RT25E_RATIO, 174 }; 175 176 static const struct emif_regs ddr2_emif_reg_data = { 177 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 178 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 179 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 180 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 181 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 182 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 183 }; 184 185 #define OSC (V_OSCK / 1000000) 186 const struct dpll_params dpll_ddr = { 187 266, OSC - 1, 1, -1, -1, -1, -1}; 188 const struct dpll_params dpll_ddr_evm_sk = { 189 303, OSC - 1, 1, -1, -1, -1, -1}; 190 const struct dpll_params dpll_ddr_bone_black = { 191 400, OSC - 1, 1, -1, -1, -1, -1}; 192 193 void am33xx_spl_board_init(void) 194 { 195 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 196 197 /* Get the frequency */ 198 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); 199 200 /* Set CORE Frequencies to OPP100 */ 201 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 202 203 /* Set MPU Frequency to what we detected now that voltages are set */ 204 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); 205 206 /* save boot device for later use by 'board_late_init' */ 207 save_boot_device(); 208 } 209 210 const struct dpll_params *get_dpll_ddr_params(void) 211 { 212 enable_i2c0_pin_mux(); 213 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 214 215 return &dpll_ddr; 216 } 217 218 void set_mux_conf_regs(void) 219 { 220 /* done first by the ROM and afterwards by the pin controller driver */ 221 enable_i2c0_pin_mux(); 222 } 223 224 const struct ctrl_ioregs ioregs = { 225 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 226 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 227 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 228 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 229 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 230 }; 231 232 void sdram_init(void) 233 { 234 config_ddr(266, &ioregs, &ddr2_data, 235 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); 236 } 237 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 238 239 #ifdef CONFIG_DEBUG_UART 240 void board_debug_uart_init(void) 241 { 242 /* done by pin controller driver if not debugging */ 243 enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE); 244 } 245 #endif 246 247 /* 248 * Basic board specific setup. Pinmux has been handled already. 249 */ 250 int board_init(void) 251 { 252 #ifdef CONFIG_HW_WATCHDOG 253 hw_watchdog_init(); 254 #endif 255 256 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 257 return 0; 258 } 259 260 #ifdef CONFIG_BOARD_LATE_INIT 261 int board_late_init(void) 262 { 263 struct udevice *dev; 264 265 set_mpu_and_core_voltage(); 266 env_set_boot_device(); 267 268 /* second I2C bus connects to node ID and front panel LED chip */ 269 if (!i2c_get_chip_for_busnum(1, I2C_ADDR_LEDS, 1, &dev)) 270 set_run_led(dev); 271 if (!i2c_get_chip_for_busnum(1, I2C_ADDR_NODE_ID, 1, &dev)) 272 env_set_serial(dev); 273 274 return 0; 275 } 276 #endif 277