1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * DHCOM DH-iMX6 PDK SPL support 4 * 5 * Copyright (C) 2017 Marek Vasut <marex@denx.de> 6 */ 7 8 #include <common.h> 9 #include <asm/arch/clock.h> 10 #include <asm/arch/crm_regs.h> 11 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/iomux.h> 13 #include <asm/arch/mx6-ddr.h> 14 #include <asm/arch/mx6-pins.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/gpio.h> 17 #include <asm/mach-imx/boot_mode.h> 18 #include <asm/mach-imx/iomux-v3.h> 19 #include <asm/mach-imx/mxc_i2c.h> 20 #include <asm/io.h> 21 #include <errno.h> 22 #include <fuse.h> 23 #include <fsl_esdhc.h> 24 #include <i2c.h> 25 #include <mmc.h> 26 #include <spl.h> 27 28 #define ENET_PAD_CTRL \ 29 (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 30 PAD_CTL_HYS) 31 32 #define GPIO_PAD_CTRL \ 33 (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) 34 35 #define SPI_PAD_CTRL \ 36 (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 37 PAD_CTL_SRE_FAST) 38 39 #define UART_PAD_CTRL \ 40 (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 41 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 42 43 #define USDHC_PAD_CTRL \ 44 (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 45 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 46 47 static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = { 48 .dram_sdclk_0 = 0x00020030, 49 .dram_sdclk_1 = 0x00020030, 50 .dram_cas = 0x00020030, 51 .dram_ras = 0x00020030, 52 .dram_reset = 0x00020030, 53 .dram_sdcke0 = 0x00003000, 54 .dram_sdcke1 = 0x00003000, 55 .dram_sdba2 = 0x00000000, 56 .dram_sdodt0 = 0x00003030, 57 .dram_sdodt1 = 0x00003030, 58 .dram_sdqs0 = 0x00000030, 59 .dram_sdqs1 = 0x00000030, 60 .dram_sdqs2 = 0x00000030, 61 .dram_sdqs3 = 0x00000030, 62 .dram_sdqs4 = 0x00000030, 63 .dram_sdqs5 = 0x00000030, 64 .dram_sdqs6 = 0x00000030, 65 .dram_sdqs7 = 0x00000030, 66 .dram_dqm0 = 0x00020030, 67 .dram_dqm1 = 0x00020030, 68 .dram_dqm2 = 0x00020030, 69 .dram_dqm3 = 0x00020030, 70 .dram_dqm4 = 0x00020030, 71 .dram_dqm5 = 0x00020030, 72 .dram_dqm6 = 0x00020030, 73 .dram_dqm7 = 0x00020030, 74 }; 75 76 static const struct mx6dq_iomux_grp_regs dhcom6dq_grp_ioregs = { 77 .grp_ddr_type = 0x000C0000, 78 .grp_ddrmode_ctl = 0x00020000, 79 .grp_ddrpke = 0x00000000, 80 .grp_addds = 0x00000030, 81 .grp_ctlds = 0x00000030, 82 .grp_ddrmode = 0x00020000, 83 .grp_b0ds = 0x00000030, 84 .grp_b1ds = 0x00000030, 85 .grp_b2ds = 0x00000030, 86 .grp_b3ds = 0x00000030, 87 .grp_b4ds = 0x00000030, 88 .grp_b5ds = 0x00000030, 89 .grp_b6ds = 0x00000030, 90 .grp_b7ds = 0x00000030, 91 }; 92 93 static const struct mx6sdl_iomux_ddr_regs dhcom6sdl_ddr_ioregs = { 94 .dram_sdclk_0 = 0x00020030, 95 .dram_sdclk_1 = 0x00020030, 96 .dram_cas = 0x00020030, 97 .dram_ras = 0x00020030, 98 .dram_reset = 0x00020030, 99 .dram_sdcke0 = 0x00003000, 100 .dram_sdcke1 = 0x00003000, 101 .dram_sdba2 = 0x00000000, 102 .dram_sdodt0 = 0x00003030, 103 .dram_sdodt1 = 0x00003030, 104 .dram_sdqs0 = 0x00000030, 105 .dram_sdqs1 = 0x00000030, 106 .dram_sdqs2 = 0x00000030, 107 .dram_sdqs3 = 0x00000030, 108 .dram_sdqs4 = 0x00000030, 109 .dram_sdqs5 = 0x00000030, 110 .dram_sdqs6 = 0x00000030, 111 .dram_sdqs7 = 0x00000030, 112 .dram_dqm0 = 0x00020030, 113 .dram_dqm1 = 0x00020030, 114 .dram_dqm2 = 0x00020030, 115 .dram_dqm3 = 0x00020030, 116 .dram_dqm4 = 0x00020030, 117 .dram_dqm5 = 0x00020030, 118 .dram_dqm6 = 0x00020030, 119 .dram_dqm7 = 0x00020030, 120 }; 121 122 static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = { 123 .grp_ddr_type = 0x000C0000, 124 .grp_ddrmode_ctl = 0x00020000, 125 .grp_ddrpke = 0x00000000, 126 .grp_addds = 0x00000030, 127 .grp_ctlds = 0x00000030, 128 .grp_ddrmode = 0x00020000, 129 .grp_b0ds = 0x00000030, 130 .grp_b1ds = 0x00000030, 131 .grp_b2ds = 0x00000030, 132 .grp_b3ds = 0x00000030, 133 .grp_b4ds = 0x00000030, 134 .grp_b5ds = 0x00000030, 135 .grp_b6ds = 0x00000030, 136 .grp_b7ds = 0x00000030, 137 }; 138 139 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x4g_1066 = { 140 .p0_mpwldectrl0 = 0x00150019, 141 .p0_mpwldectrl1 = 0x001C000B, 142 .p1_mpwldectrl0 = 0x00020018, 143 .p1_mpwldectrl1 = 0x0002000C, 144 .p0_mpdgctrl0 = 0x43140320, 145 .p0_mpdgctrl1 = 0x03080304, 146 .p1_mpdgctrl0 = 0x43180320, 147 .p1_mpdgctrl1 = 0x03100254, 148 .p0_mprddlctl = 0x4830383C, 149 .p1_mprddlctl = 0x3836323E, 150 .p0_mpwrdlctl = 0x3E444642, 151 .p1_mpwrdlctl = 0x42344442, 152 }; 153 154 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = { 155 .p0_mpwldectrl0 = 0x0040003C, 156 .p0_mpwldectrl1 = 0x0032003E, 157 .p0_mpdgctrl0 = 0x42350231, 158 .p0_mpdgctrl1 = 0x021A0218, 159 .p0_mprddlctl = 0x4B4B4E49, 160 .p0_mpwrdlctl = 0x3F3F3035, 161 }; 162 163 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = { 164 .p0_mpwldectrl0 = 0x0011000E, 165 .p0_mpwldectrl1 = 0x000E001B, 166 .p1_mpwldectrl0 = 0x00190015, 167 .p1_mpwldectrl1 = 0x00070018, 168 .p0_mpdgctrl0 = 0x42720306, 169 .p0_mpdgctrl1 = 0x026F0266, 170 .p1_mpdgctrl0 = 0x4273030A, 171 .p1_mpdgctrl1 = 0x02740240, 172 .p0_mprddlctl = 0x45393B3E, 173 .p1_mprddlctl = 0x403A3747, 174 .p0_mpwrdlctl = 0x40434541, 175 .p1_mpwrdlctl = 0x473E4A3B, 176 }; 177 178 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = { 179 .p0_mpwldectrl0 = 0x003A003A, 180 .p0_mpwldectrl1 = 0x0030002F, 181 .p1_mpwldectrl0 = 0x002F0038, 182 .p1_mpwldectrl1 = 0x00270039, 183 .p0_mpdgctrl0 = 0x420F020F, 184 .p0_mpdgctrl1 = 0x01760175, 185 .p1_mpdgctrl0 = 0x41640171, 186 .p1_mpdgctrl1 = 0x015E0160, 187 .p0_mprddlctl = 0x45464B4A, 188 .p1_mprddlctl = 0x49484A46, 189 .p0_mpwrdlctl = 0x40402E32, 190 .p1_mpwrdlctl = 0x3A3A3231, 191 }; 192 193 static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x2g_800 = { 194 .p0_mpwldectrl0 = 0x0040003C, 195 .p0_mpwldectrl1 = 0x0032003E, 196 .p0_mpdgctrl0 = 0x42350231, 197 .p0_mpdgctrl1 = 0x021A0218, 198 .p0_mprddlctl = 0x4B4B4E49, 199 .p0_mpwrdlctl = 0x3F3F3035, 200 }; 201 202 /* 203 * 2 Gbit DDR3 memory 204 * - NANYA #NT5CC128M16IP-DII 205 * - NANYA #NT5CB128M16FP-DII 206 */ 207 static const struct mx6_ddr3_cfg dhcom_mem_ddr_2g = { 208 .mem_speed = 1600, 209 .density = 2, 210 .width = 16, 211 .banks = 8, 212 .rowaddr = 14, 213 .coladdr = 10, 214 .pagesz = 2, 215 .trcd = 1375, 216 .trcmin = 5863, 217 .trasmin = 3750, 218 }; 219 220 /* 221 * 4 Gbit DDR3 memory 222 * - Intelligent Memory #IM4G16D3EABG-125I 223 */ 224 static const struct mx6_ddr3_cfg dhcom_mem_ddr_4g = { 225 .mem_speed = 1600, 226 .density = 4, 227 .width = 16, 228 .banks = 8, 229 .rowaddr = 15, 230 .coladdr = 10, 231 .pagesz = 2, 232 .trcd = 1375, 233 .trcmin = 4875, 234 .trasmin = 3500, 235 }; 236 237 /* DDR3 64bit */ 238 static const struct mx6_ddr_sysinfo dhcom_ddr_64bit = { 239 /* width of data bus:0=16,1=32,2=64 */ 240 .dsize = 2, 241 .cs_density = 32, 242 .ncs = 1, /* single chip select */ 243 .cs1_mirror = 1, 244 .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */ 245 .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */ 246 .walat = 1, /* Write additional latency */ 247 .ralat = 5, /* Read additional latency */ 248 .mif3_mode = 3, /* Command prediction working mode */ 249 .bi_on = 1, /* Bank interleaving enabled */ 250 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 251 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 252 .refsel = 1, /* Refresh cycles at 32KHz */ 253 .refr = 3, /* 4 refresh commands per refresh cycle */ 254 }; 255 256 /* DDR3 32bit */ 257 static const struct mx6_ddr_sysinfo dhcom_ddr_32bit = { 258 /* width of data bus:0=16,1=32,2=64 */ 259 .dsize = 1, 260 .cs_density = 32, 261 .ncs = 1, /* single chip select */ 262 .cs1_mirror = 1, 263 .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */ 264 .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */ 265 .walat = 1, /* Write additional latency */ 266 .ralat = 5, /* Read additional latency */ 267 .mif3_mode = 3, /* Command prediction working mode */ 268 .bi_on = 1, /* Bank interleaving enabled */ 269 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 270 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 271 .refsel = 1, /* Refresh cycles at 32KHz */ 272 .refr = 3, /* 4 refresh commands per refresh cycle */ 273 }; 274 275 static void ccgr_init(void) 276 { 277 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 278 279 writel(0x00C03F3F, &ccm->CCGR0); 280 writel(0x0030FC03, &ccm->CCGR1); 281 writel(0x0FFFC000, &ccm->CCGR2); 282 writel(0x3FF00000, &ccm->CCGR3); 283 writel(0x00FFF300, &ccm->CCGR4); 284 writel(0x0F0000C3, &ccm->CCGR5); 285 writel(0x000003FF, &ccm->CCGR6); 286 } 287 288 /* Board ID */ 289 static iomux_v3_cfg_t const hwcode_pads[] = { 290 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 291 IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 292 IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 293 }; 294 295 static void setup_iomux_boardid(void) 296 { 297 /* HW code pins: Setup alternate function and configure pads */ 298 SETUP_IOMUX_PADS(hwcode_pads); 299 } 300 301 /* DDR Code */ 302 static iomux_v3_cfg_t const ddrcode_pads[] = { 303 IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 304 IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 305 }; 306 307 static void setup_iomux_ddrcode(void) 308 { 309 /* ddr code pins */ 310 SETUP_IOMUX_PADS(ddrcode_pads); 311 } 312 313 enum dhcom_ddr3_code { 314 DH_DDR3_SIZE_256MIB = 0x00, 315 DH_DDR3_SIZE_512MIB = 0x01, 316 DH_DDR3_SIZE_1GIB = 0x02, 317 DH_DDR3_SIZE_2GIB = 0x03 318 }; 319 320 #define DDR3_CODE_BIT_0 IMX_GPIO_NR(2, 22) 321 #define DDR3_CODE_BIT_1 IMX_GPIO_NR(2, 21) 322 323 enum dhcom_ddr3_code dhcom_get_ddr3_code(void) 324 { 325 enum dhcom_ddr3_code ddr3_code; 326 327 gpio_request(DDR3_CODE_BIT_0, "DDR3_CODE_BIT_0"); 328 gpio_request(DDR3_CODE_BIT_1, "DDR3_CODE_BIT_1"); 329 330 gpio_direction_input(DDR3_CODE_BIT_0); 331 gpio_direction_input(DDR3_CODE_BIT_1); 332 333 /* 256MB = 0b00; 512MB = 0b01; 1GB = 0b10; 2GB = 0b11 */ 334 ddr3_code = (!!gpio_get_value(DDR3_CODE_BIT_1) << 1) 335 | (!!gpio_get_value(DDR3_CODE_BIT_0)); 336 337 return ddr3_code; 338 } 339 340 /* GPIO */ 341 static iomux_v3_cfg_t const gpio_pads[] = { 342 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 343 IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 344 IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 345 IOMUX_PADS(PAD_CSI0_DAT17__GPIO6_IO03 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 346 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 347 IOMUX_PADS(PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 348 IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 349 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 350 IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 351 IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 352 IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 353 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 354 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 355 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 356 IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 357 IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 358 IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 359 IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 360 IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 361 IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 362 IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 363 IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 364 IOMUX_PADS(PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), 365 }; 366 367 static void setup_iomux_gpio(void) 368 { 369 SETUP_IOMUX_PADS(gpio_pads); 370 } 371 372 /* Ethernet */ 373 static iomux_v3_cfg_t const enet_pads[] = { 374 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), 375 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 376 IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)), 377 IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 378 IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 379 IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), 380 IOMUX_PADS(PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL)), 381 IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 382 IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 383 IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)), 384 /* SMSC PHY Reset */ 385 IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), 386 /* ENET_VIO_GPIO */ 387 IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)), 388 /* ENET_Interrupt - (not used) */ 389 IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), 390 }; 391 392 static void setup_iomux_enet(void) 393 { 394 SETUP_IOMUX_PADS(enet_pads); 395 } 396 397 /* SD interface */ 398 static iomux_v3_cfg_t const usdhc2_pads[] = { 399 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 400 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 401 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 402 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 403 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 404 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 405 IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */ 406 }; 407 408 /* onboard microSD */ 409 static iomux_v3_cfg_t const usdhc3_pads[] = { 410 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 411 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 412 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 413 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 414 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 415 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 416 IOMUX_PADS(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */ 417 }; 418 419 /* eMMC */ 420 static iomux_v3_cfg_t const usdhc4_pads[] = { 421 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 422 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 423 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 424 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 425 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 426 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 427 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 428 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 429 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 430 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 431 }; 432 433 /* SD */ 434 static void setup_iomux_sd(void) 435 { 436 SETUP_IOMUX_PADS(usdhc2_pads); 437 SETUP_IOMUX_PADS(usdhc3_pads); 438 SETUP_IOMUX_PADS(usdhc4_pads); 439 } 440 441 /* SPI */ 442 static iomux_v3_cfg_t const ecspi1_pads[] = { 443 /* SS0 */ 444 IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL)), 445 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), 446 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), 447 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), 448 }; 449 450 static void setup_iomux_spi(void) 451 { 452 SETUP_IOMUX_PADS(ecspi1_pads); 453 } 454 455 int board_spi_cs_gpio(unsigned bus, unsigned cs) 456 { 457 if (bus == 0 && cs == 0) 458 return IMX_GPIO_NR(2, 30); 459 else 460 return -1; 461 } 462 463 /* UART */ 464 static iomux_v3_cfg_t const uart1_pads[] = { 465 IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 466 IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 467 }; 468 469 static void setup_iomux_uart(void) 470 { 471 SETUP_IOMUX_PADS(uart1_pads); 472 } 473 474 /* USB */ 475 static iomux_v3_cfg_t const usb_pads[] = { 476 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)), 477 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), 478 }; 479 480 static void setup_iomux_usb(void) 481 { 482 SETUP_IOMUX_PADS(usb_pads); 483 } 484 485 486 /* DRAM */ 487 static void dhcom_spl_dram_init(void) 488 { 489 enum dhcom_ddr3_code ddr3_code = dhcom_get_ddr3_code(); 490 491 if (is_mx6dq()) { 492 mx6dq_dram_iocfg(64, &dhcom6dq_ddr_ioregs, 493 &dhcom6dq_grp_ioregs); 494 switch (ddr3_code) { 495 default: 496 printf("imx6qd: unsupported ddr3 code %d\n", ddr3_code); 497 printf(" choosing 1024 MB\n"); 498 /* fall through */ 499 case DH_DDR3_SIZE_1GIB: 500 mx6_dram_cfg(&dhcom_ddr_64bit, 501 &dhcom_mmdc_calib_4x2g_1066, 502 &dhcom_mem_ddr_2g); 503 break; 504 case DH_DDR3_SIZE_2GIB: 505 mx6_dram_cfg(&dhcom_ddr_64bit, 506 &dhcom_mmdc_calib_4x4g_1066, 507 &dhcom_mem_ddr_4g); 508 break; 509 } 510 511 /* Perform DDR DRAM calibration */ 512 udelay(100); 513 mmdc_do_dqs_calibration(&dhcom_ddr_64bit); 514 515 } else if (is_cpu_type(MXC_CPU_MX6DL)) { 516 mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs, 517 &dhcom6sdl_grp_ioregs); 518 switch (ddr3_code) { 519 default: 520 printf("imx6dl: unsupported ddr3 code %d\n", ddr3_code); 521 printf(" choosing 1024 MB\n"); 522 /* fall through */ 523 case DH_DDR3_SIZE_1GIB: 524 mx6_dram_cfg(&dhcom_ddr_64bit, 525 &dhcom_mmdc_calib_4x2g_800, 526 &dhcom_mem_ddr_2g); 527 break; 528 } 529 530 /* Perform DDR DRAM calibration */ 531 udelay(100); 532 mmdc_do_dqs_calibration(&dhcom_ddr_64bit); 533 534 } else if (is_cpu_type(MXC_CPU_MX6SOLO)) { 535 mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs, 536 &dhcom6sdl_grp_ioregs); 537 switch (ddr3_code) { 538 default: 539 printf("imx6s: unsupported ddr3 code %d\n", ddr3_code); 540 printf(" choosing 512 MB\n"); 541 /* fall through */ 542 case DH_DDR3_SIZE_512MIB: 543 mx6_dram_cfg(&dhcom_ddr_32bit, 544 &dhcom_mmdc_calib_2x2g_800, 545 &dhcom_mem_ddr_2g); 546 break; 547 case DH_DDR3_SIZE_1GIB: 548 mx6_dram_cfg(&dhcom_ddr_32bit, 549 &dhcom_mmdc_calib_2x4g_800, 550 &dhcom_mem_ddr_4g); 551 break; 552 } 553 554 /* Perform DDR DRAM calibration */ 555 udelay(100); 556 mmdc_do_dqs_calibration(&dhcom_ddr_32bit); 557 } 558 } 559 560 void board_init_f(ulong dummy) 561 { 562 /* setup AIPS and disable watchdog */ 563 arch_cpu_init(); 564 565 ccgr_init(); 566 gpr_init(); 567 568 /* setup GP timer */ 569 timer_init(); 570 571 setup_iomux_boardid(); 572 setup_iomux_ddrcode(); 573 setup_iomux_gpio(); 574 setup_iomux_enet(); 575 setup_iomux_sd(); 576 setup_iomux_spi(); 577 setup_iomux_uart(); 578 setup_iomux_usb(); 579 580 /* UART clocks enabled and gd valid - init serial console */ 581 preloader_console_init(); 582 583 /* DDR3 initialization */ 584 dhcom_spl_dram_init(); 585 586 /* Clear the BSS. */ 587 memset(__bss_start, 0, __bss_end - __bss_start); 588 589 /* load/boot image from boot device */ 590 board_init_r(NULL, 0); 591 } 592