xref: /openbmc/u-boot/board/davinci/ea20/ea20.c (revision ca1646b8)
1649a33e4SStefano Babic /*
2649a33e4SStefano Babic  * (C) Copyright 2010
3649a33e4SStefano Babic  * Stefano Babic, DENX Software Engineering, sbabic@denx.de
4649a33e4SStefano Babic  *
5649a33e4SStefano Babic  * Based on da850evm.c, original Copyrights follow:
6649a33e4SStefano Babic  *
7649a33e4SStefano Babic  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
8649a33e4SStefano Babic  *
9649a33e4SStefano Babic  * Based on da830evm.c. Original Copyrights follow:
10649a33e4SStefano Babic  *
11649a33e4SStefano Babic  * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
12649a33e4SStefano Babic  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
13649a33e4SStefano Babic  *
14649a33e4SStefano Babic  * This program is free software; you can redistribute it and/or modify
15649a33e4SStefano Babic  * it under the terms of the GNU General Public License as published by
16649a33e4SStefano Babic  * the Free Software Foundation; either version 2 of the License, or
17649a33e4SStefano Babic  * (at your option) any later version.
18649a33e4SStefano Babic  *
19649a33e4SStefano Babic  * This program is distributed in the hope that it will be useful,
20649a33e4SStefano Babic  * but WITHOUT ANY WARRANTY; without even the implied warranty of
21649a33e4SStefano Babic  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22649a33e4SStefano Babic  * GNU General Public License for more details.
23649a33e4SStefano Babic  *
24649a33e4SStefano Babic  * You should have received a copy of the GNU General Public License
25649a33e4SStefano Babic  * along with this program; if not, write to the Free Software
26649a33e4SStefano Babic  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27649a33e4SStefano Babic  */
28649a33e4SStefano Babic 
29649a33e4SStefano Babic #include <common.h>
30649a33e4SStefano Babic #include <i2c.h>
31649a33e4SStefano Babic #include <net.h>
32649a33e4SStefano Babic #include <netdev.h>
33649a33e4SStefano Babic #include <asm/arch/hardware.h>
34649a33e4SStefano Babic #include <asm/arch/emif_defs.h>
35649a33e4SStefano Babic #include <asm/arch/emac_defs.h>
36649a33e4SStefano Babic #include <asm/io.h>
37649a33e4SStefano Babic #include <asm/arch/davinci_misc.h>
38*ca1646b8SBastian Ruppert #include <asm/arch/gpio.h>
39649a33e4SStefano Babic 
40649a33e4SStefano Babic DECLARE_GLOBAL_DATA_PTR;
41649a33e4SStefano Babic 
42649a33e4SStefano Babic #define pinmux(x)	(&davinci_syscfg_regs->pinmux[x])
43649a33e4SStefano Babic 
44649a33e4SStefano Babic /* SPI0 pin muxer settings */
45649a33e4SStefano Babic static const struct pinmux_config spi1_pins[] = {
46649a33e4SStefano Babic 	{ pinmux(5), 1, 1 },
47649a33e4SStefano Babic 	{ pinmux(5), 1, 2 },
48649a33e4SStefano Babic 	{ pinmux(5), 1, 4 },
49649a33e4SStefano Babic 	{ pinmux(5), 1, 5 }
50649a33e4SStefano Babic };
51649a33e4SStefano Babic 
52f9fc237fSBastian Ruppert /* UART0 pin muxer settings */
53649a33e4SStefano Babic static const struct pinmux_config uart_pins[] = {
54f9fc237fSBastian Ruppert 	{ pinmux(3), 2, 7 },
55f9fc237fSBastian Ruppert 	{ pinmux(3), 2, 6 },
56f9fc237fSBastian Ruppert 	{ pinmux(3), 2, 4 },
57f9fc237fSBastian Ruppert 	{ pinmux(3), 2, 5 }
58649a33e4SStefano Babic };
59649a33e4SStefano Babic 
60649a33e4SStefano Babic #ifdef CONFIG_DRIVER_TI_EMAC
61649a33e4SStefano Babic #define HAS_RMII 1
62649a33e4SStefano Babic static const struct pinmux_config emac_pins[] = {
63649a33e4SStefano Babic 	{ pinmux(14), 8, 2 },
64649a33e4SStefano Babic 	{ pinmux(14), 8, 3 },
65649a33e4SStefano Babic 	{ pinmux(14), 8, 4 },
66649a33e4SStefano Babic 	{ pinmux(14), 8, 5 },
67649a33e4SStefano Babic 	{ pinmux(14), 8, 6 },
68649a33e4SStefano Babic 	{ pinmux(14), 8, 7 },
69649a33e4SStefano Babic 	{ pinmux(15), 8, 1 },
70649a33e4SStefano Babic 	{ pinmux(4), 8, 0 },
71649a33e4SStefano Babic 	{ pinmux(4), 8, 1 }
72649a33e4SStefano Babic };
73649a33e4SStefano Babic #endif
74649a33e4SStefano Babic 
75649a33e4SStefano Babic #ifdef CONFIG_NAND_DAVINCI
76649a33e4SStefano Babic const struct pinmux_config nand_pins[] = {
77649a33e4SStefano Babic 	{ pinmux(7), 1, 1 },
78649a33e4SStefano Babic 	{ pinmux(7), 1, 2 },
79649a33e4SStefano Babic 	{ pinmux(7), 1, 4 },
80649a33e4SStefano Babic 	{ pinmux(7), 1, 5 },
81649a33e4SStefano Babic 	{ pinmux(9), 1, 0 },
82649a33e4SStefano Babic 	{ pinmux(9), 1, 1 },
83649a33e4SStefano Babic 	{ pinmux(9), 1, 2 },
84649a33e4SStefano Babic 	{ pinmux(9), 1, 3 },
85649a33e4SStefano Babic 	{ pinmux(9), 1, 4 },
86649a33e4SStefano Babic 	{ pinmux(9), 1, 5 },
87649a33e4SStefano Babic 	{ pinmux(9), 1, 6 },
88649a33e4SStefano Babic 	{ pinmux(9), 1, 7 },
89649a33e4SStefano Babic 	{ pinmux(12), 1, 5 },
90649a33e4SStefano Babic 	{ pinmux(12), 1, 6 }
91649a33e4SStefano Babic };
92649a33e4SStefano Babic #endif
93649a33e4SStefano Babic 
94*ca1646b8SBastian Ruppert const struct pinmux_config gpio_pins[] = {
95*ca1646b8SBastian Ruppert 	{ pinmux(13), 8, 0 }, /* GPIO6[15] RESETOUTn on SOM*/
96*ca1646b8SBastian Ruppert 	{ pinmux(13), 8, 5 }, /* GPIO6[10] U0_SW0 on EA20-00101_2*/
97*ca1646b8SBastian Ruppert 	{ pinmux(13), 8, 3 }  /* GPIO6[12] U0_SW1 on EA20-00101_2*/
98*ca1646b8SBastian Ruppert };
99*ca1646b8SBastian Ruppert 
100649a33e4SStefano Babic static const struct pinmux_resource pinmuxes[] = {
101649a33e4SStefano Babic #ifdef CONFIG_SPI_FLASH
102649a33e4SStefano Babic 	PINMUX_ITEM(spi1_pins),
103649a33e4SStefano Babic #endif
104649a33e4SStefano Babic 	PINMUX_ITEM(uart_pins),
105649a33e4SStefano Babic #ifdef CONFIG_NAND_DAVINCI
106649a33e4SStefano Babic 	PINMUX_ITEM(nand_pins),
107649a33e4SStefano Babic #endif
108649a33e4SStefano Babic };
109649a33e4SStefano Babic 
110649a33e4SStefano Babic static const struct lpsc_resource lpsc[] = {
111649a33e4SStefano Babic 	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
112649a33e4SStefano Babic 	{ DAVINCI_LPSC_SPI1 },	/* Serial Flash */
113649a33e4SStefano Babic 	{ DAVINCI_LPSC_EMAC },	/* image download */
114f9fc237fSBastian Ruppert 	{ DAVINCI_LPSC_UART0 },	/* console */
115649a33e4SStefano Babic 	{ DAVINCI_LPSC_GPIO },
116649a33e4SStefano Babic };
117649a33e4SStefano Babic 
118649a33e4SStefano Babic int board_init(void)
119649a33e4SStefano Babic {
120*ca1646b8SBastian Ruppert 	struct davinci_gpio *gpio6_base =
121*ca1646b8SBastian Ruppert 			(struct davinci_gpio *)DAVINCI_GPIO_BANK67;
122*ca1646b8SBastian Ruppert 
123*ca1646b8SBastian Ruppert 	/* PinMux for GPIO */
124*ca1646b8SBastian Ruppert 	if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
125*ca1646b8SBastian Ruppert 		return 1;
126*ca1646b8SBastian Ruppert 
127*ca1646b8SBastian Ruppert 	/* Set the RESETOUTn low */
128*ca1646b8SBastian Ruppert 	writel((readl(&gpio6_base->set_data) & ~(1 << 15)),
129*ca1646b8SBastian Ruppert 		&gpio6_base->set_data);
130*ca1646b8SBastian Ruppert 	writel((readl(&gpio6_base->dir) & ~(1 << 15)), &gpio6_base->dir);
131*ca1646b8SBastian Ruppert 
132*ca1646b8SBastian Ruppert 	/* Set U0_SW0 low for UART0 as console*/
133*ca1646b8SBastian Ruppert 	writel((readl(&gpio6_base->set_data) & ~(1 << 10)),
134*ca1646b8SBastian Ruppert 		&gpio6_base->set_data);
135*ca1646b8SBastian Ruppert 	writel((readl(&gpio6_base->dir) & ~(1 << 10)), &gpio6_base->dir);
136*ca1646b8SBastian Ruppert 
137*ca1646b8SBastian Ruppert 	/* Set U0_SW1 low for UART0 as console*/
138*ca1646b8SBastian Ruppert 	writel((readl(&gpio6_base->set_data) & ~(1 << 12)),
139*ca1646b8SBastian Ruppert 		&gpio6_base->set_data);
140*ca1646b8SBastian Ruppert 	writel((readl(&gpio6_base->dir) & ~(1 << 12)), &gpio6_base->dir);
141*ca1646b8SBastian Ruppert 
142649a33e4SStefano Babic #ifndef CONFIG_USE_IRQ
143649a33e4SStefano Babic 	irq_init();
144649a33e4SStefano Babic #endif
145649a33e4SStefano Babic 
146649a33e4SStefano Babic #ifdef CONFIG_NAND_DAVINCI
147649a33e4SStefano Babic 	/*
148649a33e4SStefano Babic 	 * NAND CS setup - cycle counts based on da850evm NAND timings in the
149649a33e4SStefano Babic 	 * Linux kernel @ 25MHz EMIFA
150649a33e4SStefano Babic 	 */
151649a33e4SStefano Babic 	writel((DAVINCI_ABCR_WSETUP(0) |
152649a33e4SStefano Babic 		DAVINCI_ABCR_WSTROBE(0) |
153649a33e4SStefano Babic 		DAVINCI_ABCR_WHOLD(0) |
154649a33e4SStefano Babic 		DAVINCI_ABCR_RSETUP(0) |
155649a33e4SStefano Babic 		DAVINCI_ABCR_RSTROBE(1) |
156649a33e4SStefano Babic 		DAVINCI_ABCR_RHOLD(0) |
157649a33e4SStefano Babic 		DAVINCI_ABCR_TA(0) |
158649a33e4SStefano Babic 		DAVINCI_ABCR_ASIZE_8BIT),
159649a33e4SStefano Babic 	       &davinci_emif_regs->ab2cr); /* CS3 */
160649a33e4SStefano Babic #endif
161649a33e4SStefano Babic 
162649a33e4SStefano Babic 	/* arch number of the board */
163649a33e4SStefano Babic 	gd->bd->bi_arch_number = MACH_TYPE_EA20;
164649a33e4SStefano Babic 
165649a33e4SStefano Babic 	/* address of boot parameters */
166649a33e4SStefano Babic 	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
167649a33e4SStefano Babic 
168649a33e4SStefano Babic 	/*
169649a33e4SStefano Babic 	 * Power on required peripherals
170649a33e4SStefano Babic 	 * ARM does not have access by default to PSC0 and PSC1
171649a33e4SStefano Babic 	 * assuming here that the DSP bootloader has set the IOPU
172649a33e4SStefano Babic 	 * such that PSC access is available to ARM
173649a33e4SStefano Babic 	 */
174649a33e4SStefano Babic 	if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
175649a33e4SStefano Babic 		return 1;
176649a33e4SStefano Babic 
177649a33e4SStefano Babic 	/* setup the SUSPSRC for ARM to control emulation suspend */
178649a33e4SStefano Babic 	writel(readl(&davinci_syscfg_regs->suspsrc) &
179649a33e4SStefano Babic 	       ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
180649a33e4SStefano Babic 		 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
181f9fc237fSBastian Ruppert 		 DAVINCI_SYSCFG_SUSPSRC_UART0),
182649a33e4SStefano Babic 	       &davinci_syscfg_regs->suspsrc);
183649a33e4SStefano Babic 
184649a33e4SStefano Babic 	/* configure pinmux settings */
185649a33e4SStefano Babic 	if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
186649a33e4SStefano Babic 		return 1;
187649a33e4SStefano Babic 
188649a33e4SStefano Babic #ifdef CONFIG_DRIVER_TI_EMAC
189649a33e4SStefano Babic 	if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
190649a33e4SStefano Babic 		return 1;
191649a33e4SStefano Babic 
192649a33e4SStefano Babic 	davinci_emac_mii_mode_sel(HAS_RMII);
193649a33e4SStefano Babic #endif /* CONFIG_DRIVER_TI_EMAC */
194649a33e4SStefano Babic 
195649a33e4SStefano Babic 	/* enable the console UART */
196649a33e4SStefano Babic 	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
197649a33e4SStefano Babic 		DAVINCI_UART_PWREMU_MGMT_UTRST),
198f9fc237fSBastian Ruppert 	       &davinci_uart0_ctrl_regs->pwremu_mgmt);
199649a33e4SStefano Babic 
200649a33e4SStefano Babic 	return 0;
201649a33e4SStefano Babic }
202649a33e4SStefano Babic 
203649a33e4SStefano Babic #ifdef CONFIG_DRIVER_TI_EMAC
204649a33e4SStefano Babic 
205649a33e4SStefano Babic /*
206649a33e4SStefano Babic  * Initializes on-board ethernet controllers.
207649a33e4SStefano Babic  */
208649a33e4SStefano Babic int board_eth_init(bd_t *bis)
209649a33e4SStefano Babic {
210649a33e4SStefano Babic 	if (!davinci_emac_initialize()) {
211649a33e4SStefano Babic 		printf("Error: Ethernet init failed!\n");
212649a33e4SStefano Babic 		return -1;
213649a33e4SStefano Babic 	}
214649a33e4SStefano Babic 
215649a33e4SStefano Babic 	/*
216649a33e4SStefano Babic 	 * This board has a RMII PHY. However, the MDC line on the SOM
217649a33e4SStefano Babic 	 * must not be disabled (there is no MII PHY on the
218649a33e4SStefano Babic 	 * baseboard) via the GPIO2[6], because this pin
219649a33e4SStefano Babic 	 * disables at the same time the SPI flash.
220649a33e4SStefano Babic 	 */
221649a33e4SStefano Babic 
222649a33e4SStefano Babic 	return 0;
223649a33e4SStefano Babic }
224649a33e4SStefano Babic #endif /* CONFIG_DRIVER_TI_EMAC */
225