1 /*
2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  * Based on da850evm.c. Original Copyrights follow:
5  *
6  * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
8  *
9  * SPDX-License-Identifier:	GPL-2.0+
10  */
11 
12 #include <common.h>
13 #include <i2c.h>
14 #include <net.h>
15 #include <netdev.h>
16 #include <spi.h>
17 #include <spi_flash.h>
18 #include <asm/arch/hardware.h>
19 #include <asm/ti-common/davinci_nand.h>
20 #include <asm/io.h>
21 #include <linux/errno.h>
22 #include <asm/mach-types.h>
23 #include <asm/arch/davinci_misc.h>
24 #ifdef CONFIG_MMC_DAVINCI
25 #include <mmc.h>
26 #include <asm/arch/sdmmc_defs.h>
27 #endif
28 
29 DECLARE_GLOBAL_DATA_PTR;
30 
31 #define pinmux(x)	(&davinci_syscfg_regs->pinmux[x])
32 
33 #ifdef CONFIG_MMC_DAVINCI
34 /* MMC0 pin muxer settings */
35 const struct pinmux_config mmc0_pins[] = {
36 	/* GP0[11] is required for SD to work on Rev 3 EVMs */
37 	{ pinmux(0),  8, 4 },	/* GP0[11] */
38 	{ pinmux(10), 2, 0 },	/* MMCSD0_CLK */
39 	{ pinmux(10), 2, 1 },	/* MMCSD0_CMD */
40 	{ pinmux(10), 2, 2 },	/* MMCSD0_DAT_0 */
41 	{ pinmux(10), 2, 3 },	/* MMCSD0_DAT_1 */
42 	{ pinmux(10), 2, 4 },	/* MMCSD0_DAT_2 */
43 	{ pinmux(10), 2, 5 },	/* MMCSD0_DAT_3 */
44 	/* LCDK supports only 4-bit mode, remaining pins are not configured */
45 };
46 #endif
47 
48 /* UART pin muxer settings */
49 static const struct pinmux_config uart_pins[] = {
50 	{ pinmux(0), 4, 6 },
51 	{ pinmux(0), 4, 7 },
52 	{ pinmux(4), 2, 4 },
53 	{ pinmux(4), 2, 5 }
54 };
55 
56 #ifdef CONFIG_DRIVER_TI_EMAC
57 static const struct pinmux_config emac_pins[] = {
58 	{ pinmux(2), 8, 1 },
59 	{ pinmux(2), 8, 2 },
60 	{ pinmux(2), 8, 3 },
61 	{ pinmux(2), 8, 4 },
62 	{ pinmux(2), 8, 5 },
63 	{ pinmux(2), 8, 6 },
64 	{ pinmux(2), 8, 7 },
65 	{ pinmux(3), 8, 0 },
66 	{ pinmux(3), 8, 1 },
67 	{ pinmux(3), 8, 2 },
68 	{ pinmux(3), 8, 3 },
69 	{ pinmux(3), 8, 4 },
70 	{ pinmux(3), 8, 5 },
71 	{ pinmux(3), 8, 6 },
72 	{ pinmux(3), 8, 7 },
73 	{ pinmux(4), 8, 0 },
74 	{ pinmux(4), 8, 1 }
75 };
76 #endif /* CONFIG_DRIVER_TI_EMAC */
77 
78 /* I2C pin muxer settings */
79 static const struct pinmux_config i2c_pins[] = {
80 	{ pinmux(4), 2, 2 },
81 	{ pinmux(4), 2, 3 }
82 };
83 
84 #ifdef CONFIG_NAND_DAVINCI
85 const struct pinmux_config nand_pins[] = {
86 	{ pinmux(7), 1, 1 },
87 	{ pinmux(7), 1, 2 },
88 	{ pinmux(7), 1, 4 },
89 	{ pinmux(7), 1, 5 },
90 	{ pinmux(8), 1, 0 },
91 	{ pinmux(8), 1, 1 },
92 	{ pinmux(8), 1, 2 },
93 	{ pinmux(8), 1, 3 },
94 	{ pinmux(8), 1, 4 },
95 	{ pinmux(8), 1, 5 },
96 	{ pinmux(8), 1, 6 },
97 	{ pinmux(8), 1, 7 },
98 	{ pinmux(9), 1, 0 },
99 	{ pinmux(9), 1, 1 },
100 	{ pinmux(9), 1, 2 },
101 	{ pinmux(9), 1, 3 },
102 	{ pinmux(9), 1, 4 },
103 	{ pinmux(9), 1, 5 },
104 	{ pinmux(9), 1, 6 },
105 	{ pinmux(9), 1, 7 },
106 	{ pinmux(12), 1, 5 },
107 	{ pinmux(12), 1, 6 }
108 };
109 
110 #endif
111 
112 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
113 #define HAS_RMII 1
114 #else
115 #define HAS_RMII 0
116 #endif
117 
118 const struct pinmux_resource pinmuxes[] = {
119 	PINMUX_ITEM(uart_pins),
120 	PINMUX_ITEM(i2c_pins),
121 #ifdef CONFIG_NAND_DAVINCI
122 	PINMUX_ITEM(nand_pins),
123 #endif
124 };
125 
126 const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
127 
128 const struct lpsc_resource lpsc[] = {
129 	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
130 	{ DAVINCI_LPSC_SPI1 },	/* Serial Flash */
131 	{ DAVINCI_LPSC_EMAC },	/* image download */
132 	{ DAVINCI_LPSC_UART2 },	/* console */
133 	{ DAVINCI_LPSC_GPIO },
134 #ifdef CONFIG_MMC_DAVINCI
135 	{ DAVINCI_LPSC_MMC_SD },
136 #endif
137 };
138 
139 const int lpsc_size = ARRAY_SIZE(lpsc);
140 
141 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
142 #define CONFIG_DA850_EVM_MAX_CPU_CLK	456000000
143 #endif
144 
145 /*
146  * get_board_rev() - setup to pass kernel board revision information
147  * Returns:
148  * bit[0-3]	Maximum cpu clock rate supported by onboard SoC
149  *		0000b - 300 MHz
150  *		0001b - 372 MHz
151  *		0010b - 408 MHz
152  *		0011b - 456 MHz
153  */
154 u32 get_board_rev(void)
155 {
156 	return 0;
157 }
158 
159 int board_early_init_f(void)
160 {
161 	/*
162 	 * Power on required peripherals
163 	 * ARM does not have access by default to PSC0 and PSC1
164 	 * assuming here that the DSP bootloader has set the IOPU
165 	 * such that PSC access is available to ARM
166 	 */
167 	if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
168 		return 1;
169 
170 	return 0;
171 }
172 
173 int board_init(void)
174 {
175 	irq_init();
176 
177 	/* arch number of the board */
178 	gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK;
179 
180 	/* address of boot parameters */
181 	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
182 
183 
184 	/* setup the SUSPSRC for ARM to control emulation suspend */
185 	writel(readl(&davinci_syscfg_regs->suspsrc) &
186 	       ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
187 		 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
188 		 DAVINCI_SYSCFG_SUSPSRC_UART2),
189 	       &davinci_syscfg_regs->suspsrc);
190 
191 	/* configure pinmux settings */
192 	if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
193 		return 1;
194 
195 #ifdef CONFIG_NAND_DAVINCI
196 	/*
197 	 * NAND CS setup - cycle counts based on da850evm NAND timings in the
198 	 * Linux kernel @ 25MHz EMIFA
199 	 */
200 	writel((DAVINCI_ABCR_WSETUP(15) |
201 		DAVINCI_ABCR_WSTROBE(63) |
202 		DAVINCI_ABCR_WHOLD(7) |
203 		DAVINCI_ABCR_RSETUP(15) |
204 		DAVINCI_ABCR_RSTROBE(63) |
205 		DAVINCI_ABCR_RHOLD(7) |
206 		DAVINCI_ABCR_TA(3) |
207 		DAVINCI_ABCR_ASIZE_16BIT),
208 	       &davinci_emif_regs->ab2cr); /* CS3 */
209 #endif
210 
211 
212 #ifdef CONFIG_MMC_DAVINCI
213 	if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0)
214 		return 1;
215 #endif
216 
217 #ifdef CONFIG_DRIVER_TI_EMAC
218 	if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
219 		return 1;
220 	davinci_emac_mii_mode_sel(HAS_RMII);
221 #endif /* CONFIG_DRIVER_TI_EMAC */
222 
223 	/* enable the console UART */
224 	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
225 		DAVINCI_UART_PWREMU_MGMT_UTRST),
226 	       &davinci_uart2_ctrl_regs->pwremu_mgmt);
227 
228 	return 0;
229 }
230 
231 #ifdef CONFIG_DRIVER_TI_EMAC
232 
233 /*
234  * Initializes on-board ethernet controllers.
235  */
236 int board_eth_init(bd_t *bis)
237 {
238 	if (!davinci_emac_initialize()) {
239 		printf("Error: Ethernet init failed!\n");
240 		return -1;
241 	}
242 
243 	return 0;
244 }
245 
246 #endif /* CONFIG_DRIVER_TI_EMAC */
247 
248 #define CFG_MAC_ADDR_SPI_BUS	0
249 #define CFG_MAC_ADDR_SPI_CS	0
250 #define CFG_MAC_ADDR_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
251 #define CFG_MAC_ADDR_SPI_MODE	SPI_MODE_3
252 
253 #define CFG_MAC_ADDR_OFFSET	(flash->size - SZ_64K)
254 
255 static int  get_mac_addr(u8 *addr)
256 {
257 	/* Need to find a way to get MAC ADDRESS */
258 	return 0;
259 }
260 
261 void dsp_lpsc_on(unsigned domain, unsigned int id)
262 {
263 	dv_reg_p mdstat, mdctl, ptstat, ptcmd;
264 	struct davinci_psc_regs *psc_regs;
265 
266 	psc_regs = davinci_psc0_regs;
267 	mdstat = &psc_regs->psc0.mdstat[id];
268 	mdctl = &psc_regs->psc0.mdctl[id];
269 	ptstat = &psc_regs->ptstat;
270 	ptcmd = &psc_regs->ptcmd;
271 
272 	while (*ptstat & (0x1 << domain))
273 		;
274 
275 	if ((*mdstat & 0x1f) == 0x03)
276 		return;                 /* Already on and enabled */
277 
278 	*mdctl |= 0x03;
279 
280 	*ptcmd = 0x1 << domain;
281 
282 	while (*ptstat & (0x1 << domain))
283 		;
284 	while ((*mdstat & 0x1f) != 0x03)
285 		;		/* Probably an overkill... */
286 }
287 
288 static void dspwake(void)
289 {
290 	unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
291 
292 	/* if the device is ARM only, return */
293 	if ((REG(CHIP_REV_ID_REG) & 0x3f) == 0x10)
294 		return;
295 
296 	if (!strcmp(env_get("dspwake"), "no"))
297 		return;
298 
299 	*resetvect++ = 0x1E000; /* DSP Idle */
300 	/* clear out the next 10 words as NOP */
301 	memset(resetvect, 0, sizeof(unsigned) * 10);
302 
303 	/* setup the DSP reset vector */
304 	REG(HOST1CFG) = DAVINCI_L3CBARAM_BASE;
305 
306 	dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
307 	REG(PSC0_MDCTL + (15 * 4)) |= 0x100;
308 }
309 
310 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
311 /**
312  * rmii_hw_init
313  *
314  */
315 int rmii_hw_init(void)
316 {
317 	return 0;
318 }
319 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
320 
321 int misc_init_r(void)
322 {
323 	uint8_t tmp[20], addr[10];
324 
325 
326 	if (env_get("ethaddr") == NULL) {
327 		/* Read Ethernet MAC address from EEPROM */
328 		if (dvevm_read_mac_address(addr)) {
329 			/* Set Ethernet MAC address from EEPROM */
330 			davinci_sync_env_enetaddr(addr);
331 		} else {
332 			get_mac_addr(addr);
333 		}
334 
335 		if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) {
336 			sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x",
337 				addr[0], addr[1], addr[2], addr[3], addr[4],
338 				addr[5]);
339 
340 			env_set("ethaddr", (char *)tmp);
341 		} else {
342 			printf("Invalid MAC address read.\n");
343 		}
344 	}
345 
346 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
347 	/* Select RMII fucntion through the expander */
348 	if (rmii_hw_init())
349 		printf("RMII hardware init failed!!!\n");
350 #endif
351 
352 	dspwake();
353 
354 	return 0;
355 }
356 
357 #ifdef CONFIG_MMC_DAVINCI
358 static struct davinci_mmc mmc_sd0 = {
359 	.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
360 	.host_caps = MMC_MODE_4BIT,     /* DA850 supports only 4-bit SD/MMC */
361 	.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
362 	.version = MMC_CTLR_VERSION_2,
363 };
364 
365 int board_mmc_init(bd_t *bis)
366 {
367 	mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
368 
369 	/* Add slot-0 to mmc subsystem */
370 	return davinci_mmc_init(bis, &mmc_sd0);
371 }
372 #endif
373