1 /* 2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on da850evm.c. Original Copyrights follow: 5 * 6 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <i2c.h> 14 #include <net.h> 15 #include <netdev.h> 16 #include <spi.h> 17 #include <spi_flash.h> 18 #include <asm/arch/hardware.h> 19 #include <asm/ti-common/davinci_nand.h> 20 #include <asm/io.h> 21 #include <linux/errno.h> 22 #include <asm/arch/davinci_misc.h> 23 #ifdef CONFIG_MMC_DAVINCI 24 #include <mmc.h> 25 #include <asm/arch/sdmmc_defs.h> 26 #endif 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 #define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) 31 32 #ifdef CONFIG_MMC_DAVINCI 33 /* MMC0 pin muxer settings */ 34 const struct pinmux_config mmc0_pins[] = { 35 /* GP0[11] is required for SD to work on Rev 3 EVMs */ 36 { pinmux(0), 8, 4 }, /* GP0[11] */ 37 { pinmux(10), 2, 0 }, /* MMCSD0_CLK */ 38 { pinmux(10), 2, 1 }, /* MMCSD0_CMD */ 39 { pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */ 40 { pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */ 41 { pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */ 42 { pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */ 43 /* LCDK supports only 4-bit mode, remaining pins are not configured */ 44 }; 45 #endif 46 47 /* UART pin muxer settings */ 48 static const struct pinmux_config uart_pins[] = { 49 { pinmux(0), 4, 6 }, 50 { pinmux(0), 4, 7 }, 51 { pinmux(4), 2, 4 }, 52 { pinmux(4), 2, 5 } 53 }; 54 55 #ifdef CONFIG_DRIVER_TI_EMAC 56 static const struct pinmux_config emac_pins[] = { 57 { pinmux(2), 8, 1 }, 58 { pinmux(2), 8, 2 }, 59 { pinmux(2), 8, 3 }, 60 { pinmux(2), 8, 4 }, 61 { pinmux(2), 8, 5 }, 62 { pinmux(2), 8, 6 }, 63 { pinmux(2), 8, 7 }, 64 { pinmux(3), 8, 0 }, 65 { pinmux(3), 8, 1 }, 66 { pinmux(3), 8, 2 }, 67 { pinmux(3), 8, 3 }, 68 { pinmux(3), 8, 4 }, 69 { pinmux(3), 8, 5 }, 70 { pinmux(3), 8, 6 }, 71 { pinmux(3), 8, 7 }, 72 { pinmux(4), 8, 0 }, 73 { pinmux(4), 8, 1 } 74 }; 75 #endif /* CONFIG_DRIVER_TI_EMAC */ 76 77 /* I2C pin muxer settings */ 78 static const struct pinmux_config i2c_pins[] = { 79 { pinmux(4), 2, 2 }, 80 { pinmux(4), 2, 3 } 81 }; 82 83 #ifdef CONFIG_NAND_DAVINCI 84 const struct pinmux_config nand_pins[] = { 85 { pinmux(7), 1, 1 }, 86 { pinmux(7), 1, 2 }, 87 { pinmux(7), 1, 4 }, 88 { pinmux(7), 1, 5 }, 89 { pinmux(8), 1, 0 }, 90 { pinmux(8), 1, 1 }, 91 { pinmux(8), 1, 2 }, 92 { pinmux(8), 1, 3 }, 93 { pinmux(8), 1, 4 }, 94 { pinmux(8), 1, 5 }, 95 { pinmux(8), 1, 6 }, 96 { pinmux(8), 1, 7 }, 97 { pinmux(9), 1, 0 }, 98 { pinmux(9), 1, 1 }, 99 { pinmux(9), 1, 2 }, 100 { pinmux(9), 1, 3 }, 101 { pinmux(9), 1, 4 }, 102 { pinmux(9), 1, 5 }, 103 { pinmux(9), 1, 6 }, 104 { pinmux(9), 1, 7 }, 105 { pinmux(12), 1, 5 }, 106 { pinmux(12), 1, 6 } 107 }; 108 109 #endif 110 111 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 112 #define HAS_RMII 1 113 #else 114 #define HAS_RMII 0 115 #endif 116 117 const struct pinmux_resource pinmuxes[] = { 118 PINMUX_ITEM(uart_pins), 119 PINMUX_ITEM(i2c_pins), 120 #ifdef CONFIG_NAND_DAVINCI 121 PINMUX_ITEM(nand_pins), 122 #endif 123 }; 124 125 const int pinmuxes_size = ARRAY_SIZE(pinmuxes); 126 127 const struct lpsc_resource lpsc[] = { 128 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ 129 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ 130 { DAVINCI_LPSC_EMAC }, /* image download */ 131 { DAVINCI_LPSC_UART2 }, /* console */ 132 { DAVINCI_LPSC_GPIO }, 133 #ifdef CONFIG_MMC_DAVINCI 134 { DAVINCI_LPSC_MMC_SD }, 135 #endif 136 }; 137 138 const int lpsc_size = ARRAY_SIZE(lpsc); 139 140 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK 141 #define CONFIG_DA850_EVM_MAX_CPU_CLK 456000000 142 #endif 143 144 /* 145 * get_board_rev() - setup to pass kernel board revision information 146 * Returns: 147 * bit[0-3] Maximum cpu clock rate supported by onboard SoC 148 * 0000b - 300 MHz 149 * 0001b - 372 MHz 150 * 0010b - 408 MHz 151 * 0011b - 456 MHz 152 */ 153 u32 get_board_rev(void) 154 { 155 return 0; 156 } 157 158 int board_early_init_f(void) 159 { 160 /* 161 * Power on required peripherals 162 * ARM does not have access by default to PSC0 and PSC1 163 * assuming here that the DSP bootloader has set the IOPU 164 * such that PSC access is available to ARM 165 */ 166 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) 167 return 1; 168 169 return 0; 170 } 171 172 int board_init(void) 173 { 174 #ifndef CONFIG_USE_IRQ 175 irq_init(); 176 #endif 177 178 /* address of boot parameters */ 179 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; 180 181 182 /* setup the SUSPSRC for ARM to control emulation suspend */ 183 writel(readl(&davinci_syscfg_regs->suspsrc) & 184 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | 185 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | 186 DAVINCI_SYSCFG_SUSPSRC_UART2), 187 &davinci_syscfg_regs->suspsrc); 188 189 /* configure pinmux settings */ 190 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) 191 return 1; 192 193 #ifdef CONFIG_NAND_DAVINCI 194 /* 195 * NAND CS setup - cycle counts based on da850evm NAND timings in the 196 * Linux kernel @ 25MHz EMIFA 197 */ 198 writel((DAVINCI_ABCR_WSETUP(15) | 199 DAVINCI_ABCR_WSTROBE(63) | 200 DAVINCI_ABCR_WHOLD(7) | 201 DAVINCI_ABCR_RSETUP(15) | 202 DAVINCI_ABCR_RSTROBE(63) | 203 DAVINCI_ABCR_RHOLD(7) | 204 DAVINCI_ABCR_TA(3) | 205 DAVINCI_ABCR_ASIZE_16BIT), 206 &davinci_emif_regs->ab2cr); /* CS3 */ 207 #endif 208 209 210 #ifdef CONFIG_MMC_DAVINCI 211 if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0) 212 return 1; 213 #endif 214 215 #ifdef CONFIG_DRIVER_TI_EMAC 216 if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) 217 return 1; 218 davinci_emac_mii_mode_sel(HAS_RMII); 219 #endif /* CONFIG_DRIVER_TI_EMAC */ 220 221 /* enable the console UART */ 222 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | 223 DAVINCI_UART_PWREMU_MGMT_UTRST), 224 &davinci_uart2_ctrl_regs->pwremu_mgmt); 225 226 return 0; 227 } 228 229 #ifdef CONFIG_DRIVER_TI_EMAC 230 231 /* 232 * Initializes on-board ethernet controllers. 233 */ 234 int board_eth_init(bd_t *bis) 235 { 236 if (!davinci_emac_initialize()) { 237 printf("Error: Ethernet init failed!\n"); 238 return -1; 239 } 240 241 return 0; 242 } 243 244 #endif /* CONFIG_DRIVER_TI_EMAC */ 245 246 #define CFG_MAC_ADDR_SPI_BUS 0 247 #define CFG_MAC_ADDR_SPI_CS 0 248 #define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 249 #define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3 250 251 #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K) 252 253 static int get_mac_addr(u8 *addr) 254 { 255 /* Need to find a way to get MAC ADDRESS */ 256 return 0; 257 } 258 259 void dsp_lpsc_on(unsigned domain, unsigned int id) 260 { 261 dv_reg_p mdstat, mdctl, ptstat, ptcmd; 262 struct davinci_psc_regs *psc_regs; 263 264 psc_regs = davinci_psc0_regs; 265 mdstat = &psc_regs->psc0.mdstat[id]; 266 mdctl = &psc_regs->psc0.mdctl[id]; 267 ptstat = &psc_regs->ptstat; 268 ptcmd = &psc_regs->ptcmd; 269 270 while (*ptstat & (0x1 << domain)) 271 ; 272 273 if ((*mdstat & 0x1f) == 0x03) 274 return; /* Already on and enabled */ 275 276 *mdctl |= 0x03; 277 278 *ptcmd = 0x1 << domain; 279 280 while (*ptstat & (0x1 << domain)) 281 ; 282 while ((*mdstat & 0x1f) != 0x03) 283 ; /* Probably an overkill... */ 284 } 285 286 static void dspwake(void) 287 { 288 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; 289 290 /* if the device is ARM only, return */ 291 if ((REG(CHIP_REV_ID_REG) & 0x3f) == 0x10) 292 return; 293 294 if (!strcmp(getenv("dspwake"), "no")) 295 return; 296 297 *resetvect++ = 0x1E000; /* DSP Idle */ 298 /* clear out the next 10 words as NOP */ 299 memset(resetvect, 0, sizeof(unsigned) * 10); 300 301 /* setup the DSP reset vector */ 302 REG(HOST1CFG) = DAVINCI_L3CBARAM_BASE; 303 304 dsp_lpsc_on(1, DAVINCI_LPSC_GEM); 305 REG(PSC0_MDCTL + (15 * 4)) |= 0x100; 306 } 307 308 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 309 /** 310 * rmii_hw_init 311 * 312 */ 313 int rmii_hw_init(void) 314 { 315 return 0; 316 } 317 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */ 318 319 int misc_init_r(void) 320 { 321 uint8_t tmp[20], addr[10]; 322 323 324 if (getenv("ethaddr") == NULL) { 325 /* Read Ethernet MAC address from EEPROM */ 326 if (dvevm_read_mac_address(addr)) { 327 /* Set Ethernet MAC address from EEPROM */ 328 davinci_sync_env_enetaddr(addr); 329 } else { 330 get_mac_addr(addr); 331 } 332 333 if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) { 334 sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x", 335 addr[0], addr[1], addr[2], addr[3], addr[4], 336 addr[5]); 337 338 setenv("ethaddr", (char *)tmp); 339 } else { 340 printf("Invalid MAC address read.\n"); 341 } 342 } 343 344 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 345 /* Select RMII fucntion through the expander */ 346 if (rmii_hw_init()) 347 printf("RMII hardware init failed!!!\n"); 348 #endif 349 350 dspwake(); 351 352 return 0; 353 } 354 355 #ifdef CONFIG_MMC_DAVINCI 356 static struct davinci_mmc mmc_sd0 = { 357 .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, 358 .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */ 359 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, 360 .version = MMC_CTLR_VERSION_2, 361 }; 362 363 int board_mmc_init(bd_t *bis) 364 { 365 mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID); 366 367 /* Add slot-0 to mmc subsystem */ 368 return davinci_mmc_init(bis, &mmc_sd0); 369 } 370 #endif 371