1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on da830evm.c. Original Copyrights follow: 5 * 6 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24 #include <common.h> 25 #include <i2c.h> 26 #include <net.h> 27 #include <netdev.h> 28 #include <asm/arch/hardware.h> 29 #include <asm/arch/emif_defs.h> 30 #include <asm/arch/emac_defs.h> 31 #include <asm/arch/pinmux_defs.h> 32 #include <asm/io.h> 33 #include <asm/arch/davinci_misc.h> 34 #include <hwconfig.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 #ifdef CONFIG_DRIVER_TI_EMAC 39 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 40 #define HAS_RMII 1 41 #else 42 #define HAS_RMII 0 43 #endif 44 #endif /* CONFIG_DRIVER_TI_EMAC */ 45 46 void dsp_lpsc_on(unsigned domain, unsigned int id) 47 { 48 dv_reg_p mdstat, mdctl, ptstat, ptcmd; 49 struct davinci_psc_regs *psc_regs; 50 51 psc_regs = davinci_psc0_regs; 52 mdstat = &psc_regs->psc0.mdstat[id]; 53 mdctl = &psc_regs->psc0.mdctl[id]; 54 ptstat = &psc_regs->ptstat; 55 ptcmd = &psc_regs->ptcmd; 56 57 while (*ptstat & (0x1 << domain)) 58 ; 59 60 if ((*mdstat & 0x1f) == 0x03) 61 return; /* Already on and enabled */ 62 63 *mdctl |= 0x03; 64 65 *ptcmd = 0x1 << domain; 66 67 while (*ptstat & (0x1 << domain)) 68 ; 69 while ((*mdstat & 0x1f) != 0x03) 70 ; /* Probably an overkill... */ 71 } 72 73 static void dspwake(void) 74 { 75 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; 76 u32 val; 77 78 /* if the device is ARM only, return */ 79 if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10) 80 return; 81 82 if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL)) 83 return; 84 85 *resetvect++ = 0x1E000; /* DSP Idle */ 86 /* clear out the next 10 words as NOP */ 87 memset(resetvect, 0, sizeof(unsigned) *10); 88 89 /* setup the DSP reset vector */ 90 writel(DAVINCI_L3CBARAM_BASE, HOST1CFG); 91 92 dsp_lpsc_on(1, DAVINCI_LPSC_GEM); 93 val = readl(PSC0_MDCTL + (15 * 4)); 94 val |= 0x100; 95 writel(val, (PSC0_MDCTL + (15 * 4))); 96 } 97 98 int misc_init_r(void) 99 { 100 dspwake(); 101 return 0; 102 } 103 104 static const struct pinmux_config gpio_pins[] = { 105 #ifdef CONFIG_USE_NOR 106 /* GP0[11] is required for NOR to work on Rev 3 EVMs */ 107 { pinmux(0), 8, 4 }, /* GP0[11] */ 108 #endif 109 }; 110 111 static const struct pinmux_resource pinmuxes[] = { 112 #ifdef CONFIG_DRIVER_TI_EMAC 113 PINMUX_ITEM(emac_pins_mdio), 114 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 115 PINMUX_ITEM(emac_pins_rmii), 116 #else 117 PINMUX_ITEM(emac_pins_mii), 118 #endif 119 #endif 120 #ifdef CONFIG_SPI_FLASH 121 PINMUX_ITEM(spi1_pins_base), 122 PINMUX_ITEM(spi1_pins_scs0), 123 #endif 124 PINMUX_ITEM(uart2_pins_txrx), 125 PINMUX_ITEM(uart2_pins_rtscts), 126 PINMUX_ITEM(i2c0_pins), 127 #ifdef CONFIG_NAND_DAVINCI 128 PINMUX_ITEM(emifa_pins_cs3), 129 PINMUX_ITEM(emifa_pins_cs4), 130 PINMUX_ITEM(emifa_pins_nand), 131 #elif defined(CONFIG_USE_NOR) 132 PINMUX_ITEM(emifa_pins_cs2), 133 PINMUX_ITEM(emifa_pins_nor), 134 #endif 135 PINMUX_ITEM(gpio_pins), 136 }; 137 138 static const struct lpsc_resource lpsc[] = { 139 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ 140 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ 141 { DAVINCI_LPSC_EMAC }, /* image download */ 142 { DAVINCI_LPSC_UART2 }, /* console */ 143 { DAVINCI_LPSC_GPIO }, 144 }; 145 146 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK 147 #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 148 #endif 149 150 /* 151 * get_board_rev() - setup to pass kernel board revision information 152 * Returns: 153 * bit[0-3] Maximum cpu clock rate supported by onboard SoC 154 * 0000b - 300 MHz 155 * 0001b - 372 MHz 156 * 0010b - 408 MHz 157 * 0011b - 456 MHz 158 */ 159 u32 get_board_rev(void) 160 { 161 char *s; 162 u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK; 163 u32 rev = 0; 164 165 s = getenv("maxcpuclk"); 166 if (s) 167 maxcpuclk = simple_strtoul(s, NULL, 10); 168 169 if (maxcpuclk >= 456000000) 170 rev = 3; 171 else if (maxcpuclk >= 408000000) 172 rev = 2; 173 else if (maxcpuclk >= 372000000) 174 rev = 1; 175 176 return rev; 177 } 178 179 int board_early_init_f(void) 180 { 181 /* 182 * Power on required peripherals 183 * ARM does not have access by default to PSC0 and PSC1 184 * assuming here that the DSP bootloader has set the IOPU 185 * such that PSC access is available to ARM 186 */ 187 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) 188 return 1; 189 190 return 0; 191 } 192 193 int board_init(void) 194 { 195 #ifdef CONFIG_USE_NOR 196 u32 val; 197 #endif 198 199 #ifndef CONFIG_USE_IRQ 200 irq_init(); 201 #endif 202 203 #ifdef CONFIG_NAND_DAVINCI 204 /* 205 * NAND CS setup - cycle counts based on da850evm NAND timings in the 206 * Linux kernel @ 25MHz EMIFA 207 */ 208 writel((DAVINCI_ABCR_WSETUP(0) | 209 DAVINCI_ABCR_WSTROBE(1) | 210 DAVINCI_ABCR_WHOLD(0) | 211 DAVINCI_ABCR_RSETUP(0) | 212 DAVINCI_ABCR_RSTROBE(1) | 213 DAVINCI_ABCR_RHOLD(0) | 214 DAVINCI_ABCR_TA(1) | 215 DAVINCI_ABCR_ASIZE_8BIT), 216 &davinci_emif_regs->ab2cr); /* CS3 */ 217 #endif 218 219 /* arch number of the board */ 220 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; 221 222 /* address of boot parameters */ 223 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; 224 225 /* setup the SUSPSRC for ARM to control emulation suspend */ 226 writel(readl(&davinci_syscfg_regs->suspsrc) & 227 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | 228 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | 229 DAVINCI_SYSCFG_SUSPSRC_UART2), 230 &davinci_syscfg_regs->suspsrc); 231 232 /* configure pinmux settings */ 233 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) 234 return 1; 235 236 #ifdef CONFIG_USE_NOR 237 /* Set the GPIO direction as output */ 238 clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); 239 240 /* Set the output as low */ 241 val = readl(GPIO_BANK0_REG_SET_ADDR); 242 val |= (0x01 << 11); 243 writel(val, GPIO_BANK0_REG_CLR_ADDR); 244 #endif 245 246 #ifdef CONFIG_DRIVER_TI_EMAC 247 davinci_emac_mii_mode_sel(HAS_RMII); 248 #endif /* CONFIG_DRIVER_TI_EMAC */ 249 250 /* enable the console UART */ 251 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | 252 DAVINCI_UART_PWREMU_MGMT_UTRST), 253 &davinci_uart2_ctrl_regs->pwremu_mgmt); 254 255 return 0; 256 } 257 258 #ifdef CONFIG_DRIVER_TI_EMAC 259 260 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 261 /** 262 * rmii_hw_init 263 * 264 * DA850/OMAP-L138 EVM can interface to a daughter card for 265 * additional features. This card has an I2C GPIO Expander TCA6416 266 * to select the required functions like camera, RMII Ethernet, 267 * character LCD, video. 268 * 269 * Initialization of the expander involves configuring the 270 * polarity and direction of the ports. P07-P05 are used here. 271 * These ports are connected to a Mux chip which enables only one 272 * functionality at a time. 273 * 274 * For RMII phy to respond, the MII MDIO clock has to be disabled 275 * since both the PHY devices have address as zero. The MII MDIO 276 * clock is controlled via GPIO2[6]. 277 * 278 * This code is valid for Beta version of the hardware 279 */ 280 int rmii_hw_init(void) 281 { 282 const struct pinmux_config gpio_pins[] = { 283 { pinmux(6), 8, 1 } 284 }; 285 u_int8_t buf[2]; 286 unsigned int temp; 287 int ret; 288 289 /* PinMux for GPIO */ 290 if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) 291 return 1; 292 293 /* I2C Exapnder configuration */ 294 /* Set polarity to non-inverted */ 295 buf[0] = 0x0; 296 buf[1] = 0x0; 297 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2); 298 if (ret) { 299 printf("\nExpander @ 0x%02x write FAILED!!!\n", 300 CONFIG_SYS_I2C_EXPANDER_ADDR); 301 return ret; 302 } 303 304 /* Configure P07-P05 as outputs */ 305 buf[0] = 0x1f; 306 buf[1] = 0xff; 307 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2); 308 if (ret) { 309 printf("\nExpander @ 0x%02x write FAILED!!!\n", 310 CONFIG_SYS_I2C_EXPANDER_ADDR); 311 } 312 313 /* For Ethernet RMII selection 314 * P07(SelA)=0 315 * P06(SelB)=1 316 * P05(SelC)=1 317 */ 318 if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { 319 printf("\nExpander @ 0x%02x read FAILED!!!\n", 320 CONFIG_SYS_I2C_EXPANDER_ADDR); 321 } 322 323 buf[0] &= 0x1f; 324 buf[0] |= (0 << 7) | (1 << 6) | (1 << 5); 325 if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { 326 printf("\nExpander @ 0x%02x write FAILED!!!\n", 327 CONFIG_SYS_I2C_EXPANDER_ADDR); 328 } 329 330 /* Set the output as high */ 331 temp = REG(GPIO_BANK2_REG_SET_ADDR); 332 temp |= (0x01 << 6); 333 REG(GPIO_BANK2_REG_SET_ADDR) = temp; 334 335 /* Set the GPIO direction as output */ 336 temp = REG(GPIO_BANK2_REG_DIR_ADDR); 337 temp &= ~(0x01 << 6); 338 REG(GPIO_BANK2_REG_DIR_ADDR) = temp; 339 340 return 0; 341 } 342 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */ 343 344 /* 345 * Initializes on-board ethernet controllers. 346 */ 347 int board_eth_init(bd_t *bis) 348 { 349 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 350 /* Select RMII fucntion through the expander */ 351 if (rmii_hw_init()) 352 printf("RMII hardware init failed!!!\n"); 353 #endif 354 if (!davinci_emac_initialize()) { 355 printf("Error: Ethernet init failed!\n"); 356 return -1; 357 } 358 359 return 0; 360 } 361 #endif /* CONFIG_DRIVER_TI_EMAC */ 362