1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4  *
5  * Based on da830evm.c. Original Copyrights follow:
6  *
7  * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
8  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
9  */
10 
11 #include <common.h>
12 #include <environment.h>
13 #include <i2c.h>
14 #include <net.h>
15 #include <netdev.h>
16 #include <spi.h>
17 #include <spi_flash.h>
18 #include <asm/arch/hardware.h>
19 #include <asm/ti-common/davinci_nand.h>
20 #include <asm/arch/emac_defs.h>
21 #include <asm/arch/pinmux_defs.h>
22 #include <asm/io.h>
23 #include <asm/arch/davinci_misc.h>
24 #include <linux/errno.h>
25 #include <hwconfig.h>
26 #include <asm/mach-types.h>
27 
28 #ifdef CONFIG_MMC_DAVINCI
29 #include <mmc.h>
30 #include <asm/arch/sdmmc_defs.h>
31 #endif
32 
33 DECLARE_GLOBAL_DATA_PTR;
34 
35 #ifdef CONFIG_DRIVER_TI_EMAC
36 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
37 #define HAS_RMII 1
38 #else
39 #define HAS_RMII 0
40 #endif
41 #endif /* CONFIG_DRIVER_TI_EMAC */
42 
43 #define CFG_MAC_ADDR_SPI_BUS	0
44 #define CFG_MAC_ADDR_SPI_CS	0
45 #define CFG_MAC_ADDR_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
46 #define CFG_MAC_ADDR_SPI_MODE	SPI_MODE_3
47 
48 #define CFG_MAC_ADDR_OFFSET	(flash->size - SZ_64K)
49 
50 #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
51 static int get_mac_addr(u8 *addr)
52 {
53 	struct spi_flash *flash;
54 	int ret;
55 
56 	flash = spi_flash_probe(CFG_MAC_ADDR_SPI_BUS, CFG_MAC_ADDR_SPI_CS,
57 			CFG_MAC_ADDR_SPI_MAX_HZ, CFG_MAC_ADDR_SPI_MODE);
58 	if (!flash) {
59 		printf("Error - unable to probe SPI flash.\n");
60 		return -1;
61 	}
62 
63 	ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET) + 1, 7, addr);
64 	if (ret) {
65 		printf("Error - unable to read MAC address from SPI flash.\n");
66 		return -1;
67 	}
68 
69 	return ret;
70 }
71 #endif
72 
73 void dsp_lpsc_on(unsigned domain, unsigned int id)
74 {
75 	dv_reg_p mdstat, mdctl, ptstat, ptcmd;
76 	struct davinci_psc_regs *psc_regs;
77 
78 	psc_regs = davinci_psc0_regs;
79 	mdstat = &psc_regs->psc0.mdstat[id];
80 	mdctl = &psc_regs->psc0.mdctl[id];
81 	ptstat = &psc_regs->ptstat;
82 	ptcmd = &psc_regs->ptcmd;
83 
84 	while (*ptstat & (0x1 << domain))
85 		;
86 
87 	if ((*mdstat & 0x1f) == 0x03)
88 		return;                 /* Already on and enabled */
89 
90 	*mdctl |= 0x03;
91 
92 	*ptcmd = 0x1 << domain;
93 
94 	while (*ptstat & (0x1 << domain))
95 		;
96 	while ((*mdstat & 0x1f) != 0x03)
97 		;		/* Probably an overkill... */
98 }
99 
100 static void dspwake(void)
101 {
102 	unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
103 	u32 val;
104 
105 	/* if the device is ARM only, return */
106 	if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
107 		return;
108 
109 	if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
110 		return;
111 
112 	*resetvect++ = 0x1E000; /* DSP Idle */
113 	/* clear out the next 10 words as NOP */
114 	memset(resetvect, 0, sizeof(unsigned) *10);
115 
116 	/* setup the DSP reset vector */
117 	writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
118 
119 	dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
120 	val = readl(PSC0_MDCTL + (15 * 4));
121 	val |= 0x100;
122 	writel(val, (PSC0_MDCTL + (15 * 4)));
123 }
124 
125 int misc_init_r(void)
126 {
127 	dspwake();
128 
129 #if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) || defined(CONFIG_MAC_ADDR_IN_EEPROM)
130 
131 	uchar env_enetaddr[6];
132 	int enetaddr_found;
133 
134 	enetaddr_found = eth_env_get_enetaddr("ethaddr", env_enetaddr);
135 
136 #endif
137 
138 #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
139 	int spi_mac_read;
140 	uchar buff[6];
141 
142 	spi_mac_read = get_mac_addr(buff);
143 	buff[0] = 0;
144 
145 	/*
146 	 * MAC address not present in the environment
147 	 * try and read the MAC address from SPI flash
148 	 * and set it.
149 	 */
150 	if (!enetaddr_found) {
151 		if (!spi_mac_read) {
152 			if (is_valid_ethaddr(buff)) {
153 				if (eth_env_set_enetaddr("ethaddr", buff)) {
154 					printf("Warning: Failed to "
155 					"set MAC address from SPI flash\n");
156 				}
157 			} else {
158 					printf("Warning: Invalid "
159 					"MAC address read from SPI flash\n");
160 			}
161 		}
162 	} else {
163 		/*
164 		 * MAC address present in environment compare it with
165 		 * the MAC address in SPI flash and warn on mismatch
166 		 */
167 		if (!spi_mac_read && is_valid_ethaddr(buff) &&
168 		    memcmp(env_enetaddr, buff, 6))
169 			printf("Warning: MAC address in SPI flash don't match "
170 					"with the MAC address in the environment\n");
171 		printf("Default using MAC address from environment\n");
172 	}
173 
174 #elif defined(CONFIG_MAC_ADDR_IN_EEPROM)
175 	uint8_t enetaddr[8];
176 	int eeprom_mac_read;
177 
178 	/* Read Ethernet MAC address from EEPROM */
179 	eeprom_mac_read = dvevm_read_mac_address(enetaddr);
180 
181 	/*
182 	 * MAC address not present in the environment
183 	 * try and read the MAC address from EEPROM flash
184 	 * and set it.
185 	 */
186 	if (!enetaddr_found) {
187 		if (eeprom_mac_read)
188 			/* Set Ethernet MAC address from EEPROM */
189 			davinci_sync_env_enetaddr(enetaddr);
190 	} else {
191 		/*
192 		 * MAC address present in environment compare it with
193 		 * the MAC address in EEPROM and warn on mismatch
194 		 */
195 		if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))
196 			printf("Warning: MAC address in EEPROM don't match "
197 					"with the MAC address in the environment\n");
198 		printf("Default using MAC address from environment\n");
199 	}
200 
201 #endif
202 	return 0;
203 }
204 
205 #ifdef CONFIG_MMC_DAVINCI
206 static struct davinci_mmc mmc_sd0 = {
207 	.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
208 	.host_caps = MMC_MODE_4BIT,     /* DA850 supports only 4-bit SD/MMC */
209 	.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
210 	.version = MMC_CTLR_VERSION_2,
211 };
212 
213 int board_mmc_init(bd_t *bis)
214 {
215 	mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
216 
217 	/* Add slot-0 to mmc subsystem */
218 	return davinci_mmc_init(bis, &mmc_sd0);
219 }
220 #endif
221 
222 static const struct pinmux_config gpio_pins[] = {
223 #ifdef CONFIG_USE_NOR
224 	/* GP0[11] is required for NOR to work on Rev 3 EVMs */
225 	{ pinmux(0), 8, 4 },	/* GP0[11] */
226 #endif
227 #ifdef CONFIG_MMC_DAVINCI
228 	/* GP0[11] is required for SD to work on Rev 3 EVMs */
229 	{ pinmux(0),  8, 4 },	/* GP0[11] */
230 #endif
231 };
232 
233 const struct pinmux_resource pinmuxes[] = {
234 #ifdef CONFIG_DRIVER_TI_EMAC
235 	PINMUX_ITEM(emac_pins_mdio),
236 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
237 	PINMUX_ITEM(emac_pins_rmii),
238 #else
239 	PINMUX_ITEM(emac_pins_mii),
240 #endif
241 #endif
242 #ifdef CONFIG_SPI_FLASH
243 	PINMUX_ITEM(spi1_pins_base),
244 	PINMUX_ITEM(spi1_pins_scs0),
245 #endif
246 	PINMUX_ITEM(uart2_pins_txrx),
247 	PINMUX_ITEM(uart2_pins_rtscts),
248 	PINMUX_ITEM(i2c0_pins),
249 #ifdef CONFIG_NAND_DAVINCI
250 	PINMUX_ITEM(emifa_pins_cs3),
251 	PINMUX_ITEM(emifa_pins_cs4),
252 	PINMUX_ITEM(emifa_pins_nand),
253 #elif defined(CONFIG_USE_NOR)
254 	PINMUX_ITEM(emifa_pins_cs2),
255 	PINMUX_ITEM(emifa_pins_nor),
256 #endif
257 	PINMUX_ITEM(gpio_pins),
258 #ifdef CONFIG_MMC_DAVINCI
259 	PINMUX_ITEM(mmc0_pins),
260 #endif
261 };
262 
263 const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
264 
265 const struct lpsc_resource lpsc[] = {
266 	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
267 	{ DAVINCI_LPSC_SPI1 },	/* Serial Flash */
268 	{ DAVINCI_LPSC_EMAC },	/* image download */
269 	{ DAVINCI_LPSC_UART2 },	/* console */
270 	{ DAVINCI_LPSC_GPIO },
271 #ifdef CONFIG_MMC_DAVINCI
272 	{ DAVINCI_LPSC_MMC_SD },
273 #endif
274 };
275 
276 const int lpsc_size = ARRAY_SIZE(lpsc);
277 
278 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
279 #define CONFIG_DA850_EVM_MAX_CPU_CLK	300000000
280 #endif
281 
282 #define REV_AM18X_EVM		0x100
283 
284 /*
285  * get_board_rev() - setup to pass kernel board revision information
286  * Returns:
287  * bit[0-3]	Maximum cpu clock rate supported by onboard SoC
288  *		0000b - 300 MHz
289  *		0001b - 372 MHz
290  *		0010b - 408 MHz
291  *		0011b - 456 MHz
292  */
293 u32 get_board_rev(void)
294 {
295 	char *s;
296 	u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
297 	u32 rev = 0;
298 
299 	s = env_get("maxcpuclk");
300 	if (s)
301 		maxcpuclk = simple_strtoul(s, NULL, 10);
302 
303 	if (maxcpuclk >= 456000000)
304 		rev = 3;
305 	else if (maxcpuclk >= 408000000)
306 		rev = 2;
307 	else if (maxcpuclk >= 372000000)
308 		rev = 1;
309 #ifdef CONFIG_DA850_AM18X_EVM
310 	rev |= REV_AM18X_EVM;
311 #endif
312 	return rev;
313 }
314 
315 int board_early_init_f(void)
316 {
317 	/*
318 	 * Power on required peripherals
319 	 * ARM does not have access by default to PSC0 and PSC1
320 	 * assuming here that the DSP bootloader has set the IOPU
321 	 * such that PSC access is available to ARM
322 	 */
323 	if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
324 		return 1;
325 
326 	return 0;
327 }
328 
329 int board_init(void)
330 {
331 	irq_init();
332 
333 #ifdef CONFIG_NAND_DAVINCI
334 	/*
335 	 * NAND CS setup - cycle counts based on da850evm NAND timings in the
336 	 * Linux kernel @ 25MHz EMIFA
337 	 */
338 	writel((DAVINCI_ABCR_WSETUP(2) |
339 		DAVINCI_ABCR_WSTROBE(2) |
340 		DAVINCI_ABCR_WHOLD(1) |
341 		DAVINCI_ABCR_RSETUP(1) |
342 		DAVINCI_ABCR_RSTROBE(4) |
343 		DAVINCI_ABCR_RHOLD(0) |
344 		DAVINCI_ABCR_TA(1) |
345 		DAVINCI_ABCR_ASIZE_8BIT),
346 	       &davinci_emif_regs->ab2cr); /* CS3 */
347 #endif
348 
349 	/* arch number of the board */
350 	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
351 
352 	/* address of boot parameters */
353 	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
354 
355 	/* setup the SUSPSRC for ARM to control emulation suspend */
356 	writel(readl(&davinci_syscfg_regs->suspsrc) &
357 	       ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
358 		 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
359 		 DAVINCI_SYSCFG_SUSPSRC_UART2),
360 	       &davinci_syscfg_regs->suspsrc);
361 
362 	/* configure pinmux settings */
363 	if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
364 		return 1;
365 
366 #ifdef CONFIG_USE_NOR
367 	/* Set the GPIO direction as output */
368 	clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
369 
370 	/* Set the output as low */
371 	writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR);
372 #endif
373 
374 #ifdef CONFIG_MMC_DAVINCI
375 	/* Set the GPIO direction as output */
376 	clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
377 
378 	/* Set the output as high */
379 	writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR);
380 #endif
381 
382 #ifdef CONFIG_DRIVER_TI_EMAC
383 	davinci_emac_mii_mode_sel(HAS_RMII);
384 #endif /* CONFIG_DRIVER_TI_EMAC */
385 
386 	/* enable the console UART */
387 	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
388 		DAVINCI_UART_PWREMU_MGMT_UTRST),
389 	       &davinci_uart2_ctrl_regs->pwremu_mgmt);
390 
391 	return 0;
392 }
393 
394 #ifdef CONFIG_DRIVER_TI_EMAC
395 
396 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
397 /**
398  * rmii_hw_init
399  *
400  * DA850/OMAP-L138 EVM can interface to a daughter card for
401  * additional features. This card has an I2C GPIO Expander TCA6416
402  * to select the required functions like camera, RMII Ethernet,
403  * character LCD, video.
404  *
405  * Initialization of the expander involves configuring the
406  * polarity and direction of the ports. P07-P05 are used here.
407  * These ports are connected to a Mux chip which enables only one
408  * functionality at a time.
409  *
410  * For RMII phy to respond, the MII MDIO clock has to be  disabled
411  * since both the PHY devices have address as zero. The MII MDIO
412  * clock is controlled via GPIO2[6].
413  *
414  * This code is valid for Beta version of the hardware
415  */
416 int rmii_hw_init(void)
417 {
418 	const struct pinmux_config gpio_pins[] = {
419 		{ pinmux(6), 8, 1 }
420 	};
421 	u_int8_t buf[2];
422 	unsigned int temp;
423 	int ret;
424 
425 	/* PinMux for GPIO */
426 	if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
427 		return 1;
428 
429 	/* I2C Exapnder configuration */
430 	/* Set polarity to non-inverted */
431 	buf[0] = 0x0;
432 	buf[1] = 0x0;
433 	ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
434 	if (ret) {
435 		printf("\nExpander @ 0x%02x write FAILED!!!\n",
436 				CONFIG_SYS_I2C_EXPANDER_ADDR);
437 		return ret;
438 	}
439 
440 	/* Configure P07-P05 as outputs */
441 	buf[0] = 0x1f;
442 	buf[1] = 0xff;
443 	ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
444 	if (ret) {
445 		printf("\nExpander @ 0x%02x write FAILED!!!\n",
446 				CONFIG_SYS_I2C_EXPANDER_ADDR);
447 	}
448 
449 	/* For Ethernet RMII selection
450 	 * P07(SelA)=0
451 	 * P06(SelB)=1
452 	 * P05(SelC)=1
453 	 */
454 	if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
455 		printf("\nExpander @ 0x%02x read FAILED!!!\n",
456 				CONFIG_SYS_I2C_EXPANDER_ADDR);
457 	}
458 
459 	buf[0] &= 0x1f;
460 	buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
461 	if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
462 		printf("\nExpander @ 0x%02x write FAILED!!!\n",
463 				CONFIG_SYS_I2C_EXPANDER_ADDR);
464 	}
465 
466 	/* Set the output as high */
467 	temp = REG(GPIO_BANK2_REG_SET_ADDR);
468 	temp |= (0x01 << 6);
469 	REG(GPIO_BANK2_REG_SET_ADDR) = temp;
470 
471 	/* Set the GPIO direction as output */
472 	temp = REG(GPIO_BANK2_REG_DIR_ADDR);
473 	temp &= ~(0x01 << 6);
474 	REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
475 
476 	return 0;
477 }
478 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
479 
480 /*
481  * Initializes on-board ethernet controllers.
482  */
483 int board_eth_init(bd_t *bis)
484 {
485 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
486 	/* Select RMII fucntion through the expander */
487 	if (rmii_hw_init())
488 		printf("RMII hardware init failed!!!\n");
489 #endif
490 	if (!davinci_emac_initialize()) {
491 		printf("Error: Ethernet init failed!\n");
492 		return -1;
493 	}
494 
495 	return 0;
496 }
497 #endif /* CONFIG_DRIVER_TI_EMAC */
498