1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on da830evm.c. Original Copyrights follow: 5 * 6 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <i2c.h> 14 #include <net.h> 15 #include <netdev.h> 16 #include <spi.h> 17 #include <spi_flash.h> 18 #include <asm/arch/hardware.h> 19 #include <asm/ti-common/davinci_nand.h> 20 #include <asm/arch/emac_defs.h> 21 #include <asm/arch/pinmux_defs.h> 22 #include <asm/io.h> 23 #include <asm/arch/davinci_misc.h> 24 #include <linux/errno.h> 25 #include <hwconfig.h> 26 #include <asm/mach-types.h> 27 28 #ifdef CONFIG_MMC_DAVINCI 29 #include <mmc.h> 30 #include <asm/arch/sdmmc_defs.h> 31 #endif 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 #ifdef CONFIG_DRIVER_TI_EMAC 36 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 37 #define HAS_RMII 1 38 #else 39 #define HAS_RMII 0 40 #endif 41 #endif /* CONFIG_DRIVER_TI_EMAC */ 42 43 #define CFG_MAC_ADDR_SPI_BUS 0 44 #define CFG_MAC_ADDR_SPI_CS 0 45 #define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 46 #define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3 47 48 #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K) 49 50 #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH 51 static int get_mac_addr(u8 *addr) 52 { 53 struct spi_flash *flash; 54 int ret; 55 56 flash = spi_flash_probe(CFG_MAC_ADDR_SPI_BUS, CFG_MAC_ADDR_SPI_CS, 57 CFG_MAC_ADDR_SPI_MAX_HZ, CFG_MAC_ADDR_SPI_MODE); 58 if (!flash) { 59 printf("Error - unable to probe SPI flash.\n"); 60 return -1; 61 } 62 63 ret = spi_flash_read(flash, CFG_MAC_ADDR_OFFSET, 6, addr); 64 if (ret) { 65 printf("Error - unable to read MAC address from SPI flash.\n"); 66 return -1; 67 } 68 69 return ret; 70 } 71 #endif 72 73 void dsp_lpsc_on(unsigned domain, unsigned int id) 74 { 75 dv_reg_p mdstat, mdctl, ptstat, ptcmd; 76 struct davinci_psc_regs *psc_regs; 77 78 psc_regs = davinci_psc0_regs; 79 mdstat = &psc_regs->psc0.mdstat[id]; 80 mdctl = &psc_regs->psc0.mdctl[id]; 81 ptstat = &psc_regs->ptstat; 82 ptcmd = &psc_regs->ptcmd; 83 84 while (*ptstat & (0x1 << domain)) 85 ; 86 87 if ((*mdstat & 0x1f) == 0x03) 88 return; /* Already on and enabled */ 89 90 *mdctl |= 0x03; 91 92 *ptcmd = 0x1 << domain; 93 94 while (*ptstat & (0x1 << domain)) 95 ; 96 while ((*mdstat & 0x1f) != 0x03) 97 ; /* Probably an overkill... */ 98 } 99 100 static void dspwake(void) 101 { 102 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; 103 u32 val; 104 105 /* if the device is ARM only, return */ 106 if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10) 107 return; 108 109 if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL)) 110 return; 111 112 *resetvect++ = 0x1E000; /* DSP Idle */ 113 /* clear out the next 10 words as NOP */ 114 memset(resetvect, 0, sizeof(unsigned) *10); 115 116 /* setup the DSP reset vector */ 117 writel(DAVINCI_L3CBARAM_BASE, HOST1CFG); 118 119 dsp_lpsc_on(1, DAVINCI_LPSC_GEM); 120 val = readl(PSC0_MDCTL + (15 * 4)); 121 val |= 0x100; 122 writel(val, (PSC0_MDCTL + (15 * 4))); 123 } 124 125 int misc_init_r(void) 126 { 127 dspwake(); 128 129 #if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) || defined(CONFIG_MAC_ADDR_IN_EEPROM) 130 131 uchar env_enetaddr[6]; 132 int enetaddr_found; 133 134 enetaddr_found = eth_env_get_enetaddr("ethaddr", env_enetaddr); 135 136 #endif 137 138 #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH 139 int spi_mac_read; 140 uchar buff[6]; 141 142 spi_mac_read = get_mac_addr(buff); 143 144 /* 145 * MAC address not present in the environment 146 * try and read the MAC address from SPI flash 147 * and set it. 148 */ 149 if (!enetaddr_found) { 150 if (!spi_mac_read) { 151 if (is_valid_ethaddr(buff)) { 152 if (eth_env_set_enetaddr("ethaddr", buff)) { 153 printf("Warning: Failed to " 154 "set MAC address from SPI flash\n"); 155 } 156 } else { 157 printf("Warning: Invalid " 158 "MAC address read from SPI flash\n"); 159 } 160 } 161 } else { 162 /* 163 * MAC address present in environment compare it with 164 * the MAC address in SPI flash and warn on mismatch 165 */ 166 if (!spi_mac_read && is_valid_ethaddr(buff) && 167 memcmp(env_enetaddr, buff, 6)) 168 printf("Warning: MAC address in SPI flash don't match " 169 "with the MAC address in the environment\n"); 170 printf("Default using MAC address from environment\n"); 171 } 172 173 #elif defined(CONFIG_MAC_ADDR_IN_EEPROM) 174 uint8_t enetaddr[8]; 175 int eeprom_mac_read; 176 177 /* Read Ethernet MAC address from EEPROM */ 178 eeprom_mac_read = dvevm_read_mac_address(enetaddr); 179 180 /* 181 * MAC address not present in the environment 182 * try and read the MAC address from EEPROM flash 183 * and set it. 184 */ 185 if (!enetaddr_found) { 186 if (eeprom_mac_read) 187 /* Set Ethernet MAC address from EEPROM */ 188 davinci_sync_env_enetaddr(enetaddr); 189 } else { 190 /* 191 * MAC address present in environment compare it with 192 * the MAC address in EEPROM and warn on mismatch 193 */ 194 if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6)) 195 printf("Warning: MAC address in EEPROM don't match " 196 "with the MAC address in the environment\n"); 197 printf("Default using MAC address from environment\n"); 198 } 199 200 #endif 201 return 0; 202 } 203 204 #ifdef CONFIG_MMC_DAVINCI 205 static struct davinci_mmc mmc_sd0 = { 206 .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, 207 .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */ 208 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, 209 .version = MMC_CTLR_VERSION_2, 210 }; 211 212 int board_mmc_init(bd_t *bis) 213 { 214 mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID); 215 216 /* Add slot-0 to mmc subsystem */ 217 return davinci_mmc_init(bis, &mmc_sd0); 218 } 219 #endif 220 221 static const struct pinmux_config gpio_pins[] = { 222 #ifdef CONFIG_USE_NOR 223 /* GP0[11] is required for NOR to work on Rev 3 EVMs */ 224 { pinmux(0), 8, 4 }, /* GP0[11] */ 225 #endif 226 #ifdef CONFIG_MMC_DAVINCI 227 /* GP0[11] is required for SD to work on Rev 3 EVMs */ 228 { pinmux(0), 8, 4 }, /* GP0[11] */ 229 #endif 230 }; 231 232 const struct pinmux_resource pinmuxes[] = { 233 #ifdef CONFIG_DRIVER_TI_EMAC 234 PINMUX_ITEM(emac_pins_mdio), 235 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 236 PINMUX_ITEM(emac_pins_rmii), 237 #else 238 PINMUX_ITEM(emac_pins_mii), 239 #endif 240 #endif 241 #ifdef CONFIG_SPI_FLASH 242 PINMUX_ITEM(spi1_pins_base), 243 PINMUX_ITEM(spi1_pins_scs0), 244 #endif 245 PINMUX_ITEM(uart2_pins_txrx), 246 PINMUX_ITEM(uart2_pins_rtscts), 247 PINMUX_ITEM(i2c0_pins), 248 #ifdef CONFIG_NAND_DAVINCI 249 PINMUX_ITEM(emifa_pins_cs3), 250 PINMUX_ITEM(emifa_pins_cs4), 251 PINMUX_ITEM(emifa_pins_nand), 252 #elif defined(CONFIG_USE_NOR) 253 PINMUX_ITEM(emifa_pins_cs2), 254 PINMUX_ITEM(emifa_pins_nor), 255 #endif 256 PINMUX_ITEM(gpio_pins), 257 #ifdef CONFIG_MMC_DAVINCI 258 PINMUX_ITEM(mmc0_pins), 259 #endif 260 }; 261 262 const int pinmuxes_size = ARRAY_SIZE(pinmuxes); 263 264 const struct lpsc_resource lpsc[] = { 265 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ 266 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ 267 { DAVINCI_LPSC_EMAC }, /* image download */ 268 { DAVINCI_LPSC_UART2 }, /* console */ 269 { DAVINCI_LPSC_GPIO }, 270 #ifdef CONFIG_MMC_DAVINCI 271 { DAVINCI_LPSC_MMC_SD }, 272 #endif 273 }; 274 275 const int lpsc_size = ARRAY_SIZE(lpsc); 276 277 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK 278 #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 279 #endif 280 281 #define REV_AM18X_EVM 0x100 282 283 /* 284 * get_board_rev() - setup to pass kernel board revision information 285 * Returns: 286 * bit[0-3] Maximum cpu clock rate supported by onboard SoC 287 * 0000b - 300 MHz 288 * 0001b - 372 MHz 289 * 0010b - 408 MHz 290 * 0011b - 456 MHz 291 */ 292 u32 get_board_rev(void) 293 { 294 char *s; 295 u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK; 296 u32 rev = 0; 297 298 s = env_get("maxcpuclk"); 299 if (s) 300 maxcpuclk = simple_strtoul(s, NULL, 10); 301 302 if (maxcpuclk >= 456000000) 303 rev = 3; 304 else if (maxcpuclk >= 408000000) 305 rev = 2; 306 else if (maxcpuclk >= 372000000) 307 rev = 1; 308 #ifdef CONFIG_DA850_AM18X_EVM 309 rev |= REV_AM18X_EVM; 310 #endif 311 return rev; 312 } 313 314 int board_early_init_f(void) 315 { 316 /* 317 * Power on required peripherals 318 * ARM does not have access by default to PSC0 and PSC1 319 * assuming here that the DSP bootloader has set the IOPU 320 * such that PSC access is available to ARM 321 */ 322 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) 323 return 1; 324 325 return 0; 326 } 327 328 int board_init(void) 329 { 330 irq_init(); 331 332 #ifdef CONFIG_NAND_DAVINCI 333 /* 334 * NAND CS setup - cycle counts based on da850evm NAND timings in the 335 * Linux kernel @ 25MHz EMIFA 336 */ 337 writel((DAVINCI_ABCR_WSETUP(2) | 338 DAVINCI_ABCR_WSTROBE(2) | 339 DAVINCI_ABCR_WHOLD(1) | 340 DAVINCI_ABCR_RSETUP(1) | 341 DAVINCI_ABCR_RSTROBE(4) | 342 DAVINCI_ABCR_RHOLD(0) | 343 DAVINCI_ABCR_TA(1) | 344 DAVINCI_ABCR_ASIZE_8BIT), 345 &davinci_emif_regs->ab2cr); /* CS3 */ 346 #endif 347 348 /* arch number of the board */ 349 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; 350 351 /* address of boot parameters */ 352 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; 353 354 /* setup the SUSPSRC for ARM to control emulation suspend */ 355 writel(readl(&davinci_syscfg_regs->suspsrc) & 356 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | 357 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | 358 DAVINCI_SYSCFG_SUSPSRC_UART2), 359 &davinci_syscfg_regs->suspsrc); 360 361 /* configure pinmux settings */ 362 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) 363 return 1; 364 365 #ifdef CONFIG_USE_NOR 366 /* Set the GPIO direction as output */ 367 clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); 368 369 /* Set the output as low */ 370 writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR); 371 #endif 372 373 #ifdef CONFIG_MMC_DAVINCI 374 /* Set the GPIO direction as output */ 375 clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); 376 377 /* Set the output as high */ 378 writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR); 379 #endif 380 381 #ifdef CONFIG_DRIVER_TI_EMAC 382 davinci_emac_mii_mode_sel(HAS_RMII); 383 #endif /* CONFIG_DRIVER_TI_EMAC */ 384 385 /* enable the console UART */ 386 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | 387 DAVINCI_UART_PWREMU_MGMT_UTRST), 388 &davinci_uart2_ctrl_regs->pwremu_mgmt); 389 390 return 0; 391 } 392 393 #ifdef CONFIG_DRIVER_TI_EMAC 394 395 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 396 /** 397 * rmii_hw_init 398 * 399 * DA850/OMAP-L138 EVM can interface to a daughter card for 400 * additional features. This card has an I2C GPIO Expander TCA6416 401 * to select the required functions like camera, RMII Ethernet, 402 * character LCD, video. 403 * 404 * Initialization of the expander involves configuring the 405 * polarity and direction of the ports. P07-P05 are used here. 406 * These ports are connected to a Mux chip which enables only one 407 * functionality at a time. 408 * 409 * For RMII phy to respond, the MII MDIO clock has to be disabled 410 * since both the PHY devices have address as zero. The MII MDIO 411 * clock is controlled via GPIO2[6]. 412 * 413 * This code is valid for Beta version of the hardware 414 */ 415 int rmii_hw_init(void) 416 { 417 const struct pinmux_config gpio_pins[] = { 418 { pinmux(6), 8, 1 } 419 }; 420 u_int8_t buf[2]; 421 unsigned int temp; 422 int ret; 423 424 /* PinMux for GPIO */ 425 if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) 426 return 1; 427 428 /* I2C Exapnder configuration */ 429 /* Set polarity to non-inverted */ 430 buf[0] = 0x0; 431 buf[1] = 0x0; 432 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2); 433 if (ret) { 434 printf("\nExpander @ 0x%02x write FAILED!!!\n", 435 CONFIG_SYS_I2C_EXPANDER_ADDR); 436 return ret; 437 } 438 439 /* Configure P07-P05 as outputs */ 440 buf[0] = 0x1f; 441 buf[1] = 0xff; 442 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2); 443 if (ret) { 444 printf("\nExpander @ 0x%02x write FAILED!!!\n", 445 CONFIG_SYS_I2C_EXPANDER_ADDR); 446 } 447 448 /* For Ethernet RMII selection 449 * P07(SelA)=0 450 * P06(SelB)=1 451 * P05(SelC)=1 452 */ 453 if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { 454 printf("\nExpander @ 0x%02x read FAILED!!!\n", 455 CONFIG_SYS_I2C_EXPANDER_ADDR); 456 } 457 458 buf[0] &= 0x1f; 459 buf[0] |= (0 << 7) | (1 << 6) | (1 << 5); 460 if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { 461 printf("\nExpander @ 0x%02x write FAILED!!!\n", 462 CONFIG_SYS_I2C_EXPANDER_ADDR); 463 } 464 465 /* Set the output as high */ 466 temp = REG(GPIO_BANK2_REG_SET_ADDR); 467 temp |= (0x01 << 6); 468 REG(GPIO_BANK2_REG_SET_ADDR) = temp; 469 470 /* Set the GPIO direction as output */ 471 temp = REG(GPIO_BANK2_REG_DIR_ADDR); 472 temp &= ~(0x01 << 6); 473 REG(GPIO_BANK2_REG_DIR_ADDR) = temp; 474 475 return 0; 476 } 477 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */ 478 479 /* 480 * Initializes on-board ethernet controllers. 481 */ 482 int board_eth_init(bd_t *bis) 483 { 484 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 485 /* Select RMII fucntion through the expander */ 486 if (rmii_hw_init()) 487 printf("RMII hardware init failed!!!\n"); 488 #endif 489 if (!davinci_emac_initialize()) { 490 printf("Error: Ethernet init failed!\n"); 491 return -1; 492 } 493 494 return 0; 495 } 496 #endif /* CONFIG_DRIVER_TI_EMAC */ 497