1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on da830evm.c. Original Copyrights follow: 5 * 6 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24 #include <common.h> 25 #include <i2c.h> 26 #include <net.h> 27 #include <netdev.h> 28 #include <asm/arch/hardware.h> 29 #include <asm/arch/emif_defs.h> 30 #include <asm/arch/emac_defs.h> 31 #include <asm/arch/pinmux_defs.h> 32 #include <asm/io.h> 33 #include <asm/arch/davinci_misc.h> 34 #include <hwconfig.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 #ifdef CONFIG_DRIVER_TI_EMAC 39 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 40 #define HAS_RMII 1 41 #else 42 #define HAS_RMII 0 43 #endif 44 #endif /* CONFIG_DRIVER_TI_EMAC */ 45 46 void dsp_lpsc_on(unsigned domain, unsigned int id) 47 { 48 dv_reg_p mdstat, mdctl, ptstat, ptcmd; 49 struct davinci_psc_regs *psc_regs; 50 51 psc_regs = davinci_psc0_regs; 52 mdstat = &psc_regs->psc0.mdstat[id]; 53 mdctl = &psc_regs->psc0.mdctl[id]; 54 ptstat = &psc_regs->ptstat; 55 ptcmd = &psc_regs->ptcmd; 56 57 while (*ptstat & (0x1 << domain)) 58 ; 59 60 if ((*mdstat & 0x1f) == 0x03) 61 return; /* Already on and enabled */ 62 63 *mdctl |= 0x03; 64 65 *ptcmd = 0x1 << domain; 66 67 while (*ptstat & (0x1 << domain)) 68 ; 69 while ((*mdstat & 0x1f) != 0x03) 70 ; /* Probably an overkill... */ 71 } 72 73 static void dspwake(void) 74 { 75 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; 76 u32 val; 77 78 /* if the device is ARM only, return */ 79 if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10) 80 return; 81 82 if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL)) 83 return; 84 85 *resetvect++ = 0x1E000; /* DSP Idle */ 86 /* clear out the next 10 words as NOP */ 87 memset(resetvect, 0, sizeof(unsigned) *10); 88 89 /* setup the DSP reset vector */ 90 writel(DAVINCI_L3CBARAM_BASE, HOST1CFG); 91 92 dsp_lpsc_on(1, DAVINCI_LPSC_GEM); 93 val = readl(PSC0_MDCTL + (15 * 4)); 94 val |= 0x100; 95 writel(val, (PSC0_MDCTL + (15 * 4))); 96 } 97 98 int misc_init_r(void) 99 { 100 dspwake(); 101 return 0; 102 } 103 104 static const struct pinmux_config gpio_pins[] = { 105 #ifdef CONFIG_USE_NOR 106 /* GP0[11] is required for NOR to work on Rev 3 EVMs */ 107 { pinmux(0), 8, 4 }, /* GP0[11] */ 108 #endif 109 }; 110 111 const struct pinmux_resource pinmuxes[] = { 112 #ifdef CONFIG_DRIVER_TI_EMAC 113 PINMUX_ITEM(emac_pins_mdio), 114 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 115 PINMUX_ITEM(emac_pins_rmii), 116 #else 117 PINMUX_ITEM(emac_pins_mii), 118 #endif 119 #endif 120 #ifdef CONFIG_SPI_FLASH 121 PINMUX_ITEM(spi1_pins_base), 122 PINMUX_ITEM(spi1_pins_scs0), 123 #endif 124 PINMUX_ITEM(uart2_pins_txrx), 125 PINMUX_ITEM(uart2_pins_rtscts), 126 PINMUX_ITEM(i2c0_pins), 127 #ifdef CONFIG_NAND_DAVINCI 128 PINMUX_ITEM(emifa_pins_cs3), 129 PINMUX_ITEM(emifa_pins_cs4), 130 PINMUX_ITEM(emifa_pins_nand), 131 #elif defined(CONFIG_USE_NOR) 132 PINMUX_ITEM(emifa_pins_cs2), 133 PINMUX_ITEM(emifa_pins_nor), 134 #endif 135 PINMUX_ITEM(gpio_pins), 136 }; 137 138 const int pinmuxes_size = ARRAY_SIZE(pinmuxes); 139 140 const struct lpsc_resource lpsc[] = { 141 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ 142 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ 143 { DAVINCI_LPSC_EMAC }, /* image download */ 144 { DAVINCI_LPSC_UART2 }, /* console */ 145 { DAVINCI_LPSC_GPIO }, 146 }; 147 148 const int lpsc_size = ARRAY_SIZE(lpsc); 149 150 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK 151 #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 152 #endif 153 154 #define REV_AM18X_EVM 0x100 155 156 /* 157 * get_board_rev() - setup to pass kernel board revision information 158 * Returns: 159 * bit[0-3] Maximum cpu clock rate supported by onboard SoC 160 * 0000b - 300 MHz 161 * 0001b - 372 MHz 162 * 0010b - 408 MHz 163 * 0011b - 456 MHz 164 */ 165 u32 get_board_rev(void) 166 { 167 char *s; 168 u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK; 169 u32 rev = 0; 170 171 s = getenv("maxcpuclk"); 172 if (s) 173 maxcpuclk = simple_strtoul(s, NULL, 10); 174 175 if (maxcpuclk >= 456000000) 176 rev = 3; 177 else if (maxcpuclk >= 408000000) 178 rev = 2; 179 else if (maxcpuclk >= 372000000) 180 rev = 1; 181 #ifdef CONFIG_DA850_AM18X_EVM 182 rev |= REV_AM18X_EVM; 183 #endif 184 return rev; 185 } 186 187 int board_early_init_f(void) 188 { 189 /* 190 * Power on required peripherals 191 * ARM does not have access by default to PSC0 and PSC1 192 * assuming here that the DSP bootloader has set the IOPU 193 * such that PSC access is available to ARM 194 */ 195 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) 196 return 1; 197 198 return 0; 199 } 200 201 int board_init(void) 202 { 203 #ifdef CONFIG_USE_NOR 204 u32 val; 205 #endif 206 207 #ifndef CONFIG_USE_IRQ 208 irq_init(); 209 #endif 210 211 #ifdef CONFIG_NAND_DAVINCI 212 /* 213 * NAND CS setup - cycle counts based on da850evm NAND timings in the 214 * Linux kernel @ 25MHz EMIFA 215 */ 216 writel((DAVINCI_ABCR_WSETUP(0) | 217 DAVINCI_ABCR_WSTROBE(1) | 218 DAVINCI_ABCR_WHOLD(0) | 219 DAVINCI_ABCR_RSETUP(0) | 220 DAVINCI_ABCR_RSTROBE(1) | 221 DAVINCI_ABCR_RHOLD(0) | 222 DAVINCI_ABCR_TA(1) | 223 DAVINCI_ABCR_ASIZE_8BIT), 224 &davinci_emif_regs->ab2cr); /* CS3 */ 225 #endif 226 227 /* arch number of the board */ 228 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; 229 230 /* address of boot parameters */ 231 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; 232 233 /* setup the SUSPSRC for ARM to control emulation suspend */ 234 writel(readl(&davinci_syscfg_regs->suspsrc) & 235 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | 236 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | 237 DAVINCI_SYSCFG_SUSPSRC_UART2), 238 &davinci_syscfg_regs->suspsrc); 239 240 /* configure pinmux settings */ 241 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) 242 return 1; 243 244 #ifdef CONFIG_USE_NOR 245 /* Set the GPIO direction as output */ 246 clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); 247 248 /* Set the output as low */ 249 val = readl(GPIO_BANK0_REG_SET_ADDR); 250 val |= (0x01 << 11); 251 writel(val, GPIO_BANK0_REG_CLR_ADDR); 252 #endif 253 254 #ifdef CONFIG_DRIVER_TI_EMAC 255 davinci_emac_mii_mode_sel(HAS_RMII); 256 #endif /* CONFIG_DRIVER_TI_EMAC */ 257 258 /* enable the console UART */ 259 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | 260 DAVINCI_UART_PWREMU_MGMT_UTRST), 261 &davinci_uart2_ctrl_regs->pwremu_mgmt); 262 263 return 0; 264 } 265 266 #ifdef CONFIG_DRIVER_TI_EMAC 267 268 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 269 /** 270 * rmii_hw_init 271 * 272 * DA850/OMAP-L138 EVM can interface to a daughter card for 273 * additional features. This card has an I2C GPIO Expander TCA6416 274 * to select the required functions like camera, RMII Ethernet, 275 * character LCD, video. 276 * 277 * Initialization of the expander involves configuring the 278 * polarity and direction of the ports. P07-P05 are used here. 279 * These ports are connected to a Mux chip which enables only one 280 * functionality at a time. 281 * 282 * For RMII phy to respond, the MII MDIO clock has to be disabled 283 * since both the PHY devices have address as zero. The MII MDIO 284 * clock is controlled via GPIO2[6]. 285 * 286 * This code is valid for Beta version of the hardware 287 */ 288 int rmii_hw_init(void) 289 { 290 const struct pinmux_config gpio_pins[] = { 291 { pinmux(6), 8, 1 } 292 }; 293 u_int8_t buf[2]; 294 unsigned int temp; 295 int ret; 296 297 /* PinMux for GPIO */ 298 if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) 299 return 1; 300 301 /* I2C Exapnder configuration */ 302 /* Set polarity to non-inverted */ 303 buf[0] = 0x0; 304 buf[1] = 0x0; 305 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2); 306 if (ret) { 307 printf("\nExpander @ 0x%02x write FAILED!!!\n", 308 CONFIG_SYS_I2C_EXPANDER_ADDR); 309 return ret; 310 } 311 312 /* Configure P07-P05 as outputs */ 313 buf[0] = 0x1f; 314 buf[1] = 0xff; 315 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2); 316 if (ret) { 317 printf("\nExpander @ 0x%02x write FAILED!!!\n", 318 CONFIG_SYS_I2C_EXPANDER_ADDR); 319 } 320 321 /* For Ethernet RMII selection 322 * P07(SelA)=0 323 * P06(SelB)=1 324 * P05(SelC)=1 325 */ 326 if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { 327 printf("\nExpander @ 0x%02x read FAILED!!!\n", 328 CONFIG_SYS_I2C_EXPANDER_ADDR); 329 } 330 331 buf[0] &= 0x1f; 332 buf[0] |= (0 << 7) | (1 << 6) | (1 << 5); 333 if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { 334 printf("\nExpander @ 0x%02x write FAILED!!!\n", 335 CONFIG_SYS_I2C_EXPANDER_ADDR); 336 } 337 338 /* Set the output as high */ 339 temp = REG(GPIO_BANK2_REG_SET_ADDR); 340 temp |= (0x01 << 6); 341 REG(GPIO_BANK2_REG_SET_ADDR) = temp; 342 343 /* Set the GPIO direction as output */ 344 temp = REG(GPIO_BANK2_REG_DIR_ADDR); 345 temp &= ~(0x01 << 6); 346 REG(GPIO_BANK2_REG_DIR_ADDR) = temp; 347 348 return 0; 349 } 350 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */ 351 352 /* 353 * Initializes on-board ethernet controllers. 354 */ 355 int board_eth_init(bd_t *bis) 356 { 357 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 358 /* Select RMII fucntion through the expander */ 359 if (rmii_hw_init()) 360 printf("RMII hardware init failed!!!\n"); 361 #endif 362 if (!davinci_emac_initialize()) { 363 printf("Error: Ethernet init failed!\n"); 364 return -1; 365 } 366 367 return 0; 368 } 369 #endif /* CONFIG_DRIVER_TI_EMAC */ 370